发明申请
US20120286819A1 MOS TEST STRUCTURE, METHOD FOR FORMING MOS TEST STRUCTURE AND METHOD FOR PERFORMING WAFER ACCEPTANCE TEST
有权
MOS测试结构，形成MOS测试结构的方法和执行波形接受测试的方法
- 专利标题： MOS TEST STRUCTURE, METHOD FOR FORMING MOS TEST STRUCTURE AND METHOD FOR PERFORMING WAFER ACCEPTANCE TEST
- 专利标题（中）： MOS测试结构，形成MOS测试结构的方法和执行波形接受测试的方法
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申请号： US13105913申请日： 2011-05-12
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公开(公告)号： US20120286819A1公开(公告)日： 2012-11-15
- 发明人: Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
- 申请人： Chin-Te Kuo , Yi-Nan Chen , Hsien-Wen Liu
- 主分类号： G01R31/26
- IPC分类号： G01R31/26 ; H01L21/28 ; H01L23/48
摘要：
A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.
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