公开(公告)号：US20120286819A1

公开(公告)日：2012-11-15

申请号：US13105913

申请日：2011-05-12

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: G01R31/26 ,  H01L21/28 ,  H01L23/48

CPC classification number: H01L22/34 ,  G01R31/02 ,  G01R31/26 ,  G01R31/2644 ,  G01R31/2831

Abstract: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

Abstract translation: 公开了MOS测试结构。 划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。 外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。 第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。 导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接 到外延层，使得测试通孔能够一起测试外延层和衬底。

公开(公告)号：US08912595B2

公开(公告)日：2014-12-16

申请号：US13106852

申请日：2011-05-12

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/308

CPC classification number: H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

Abstract: A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.

Abstract translation: 公开了一种沟槽MOS结构。 沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 沟槽栅极部分地设置在掺杂区域中。 沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。 两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

公开(公告)号：US08816715B2

公开(公告)日：2014-08-26

申请号：US13105913

申请日：2011-05-12

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: G01R31/02 ,  G01R31/26 ,  H01L21/66 ,  G01R31/28

CPC classification number: H01L22/34 ,  G01R31/02 ,  G01R31/26 ,  G01R31/2644 ,  G01R31/2831

Abstract: A MOS test structure is disclosed. A scribe line region is disposed on a substrate which has a first side and a second side opposite to the first side. An epitaxial layer is disposed on the first side, the doping well is disposed on the epitaxial layer and the doping region is disposed on the doping well. A trench gate of a first depth is disposed in the doping region, in the doping well and in the scribe line region. A conductive material fills the test via which has a second depth and an isolation covering the inner wall of the test via and is disposed in the doping region, in the doping well, in the epitaxial layer and in the scribe line region, to electrically connect to the epitaxial layer so that the test via is capable of testing the epitaxial layer and the substrate together.

Abstract translation: 公开了MOS测试结构。 划线区域设置在具有与第一侧相对的第一侧和第二侧的基板上。 外延层设置在第一侧上，掺杂阱设置在外延层上，并且掺杂区域设置在掺杂阱上。 第一深度的沟槽栅极设置在掺杂区域，掺杂阱和划线区域中。 导电材料填充测试，通过该测试具有覆盖测试通孔的内壁的第二深度和隔离，并且设置在掺杂区域，掺杂阱，外延层和划线区域中，以电连接 到外延层，使得测试通孔能够一起测试外延层和衬底。

公开(公告)号：US08692318B2

公开(公告)日：2014-04-08

申请号：US13104924

申请日：2011-05-10

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

Abstract translation: 提供沟槽MOS结构。 沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 沟槽设置在外延层中。 栅极隔离覆盖沟槽的内壁。 沟槽栅设置在沟槽中并且具有第一导电类型。 保护环具有第二导电类型并且设置在外延层内。 加强结构具有电绝缘材料并且设置在保护环内。

公开(公告)号：US20120286402A1

公开(公告)日：2012-11-15

申请号：US13105910

申请日：2011-05-12

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/06 ,  H01L21/302 ,  H01L23/48

CPC classification number: H01L21/0337 ,  B81B2203/0361 ,  B81B2203/0392 ,  B81C1/00103 ,  H01L21/0338 ,  H01L21/28123

Abstract: A cuboidal protuberant structure is provided. The cuboidal protuberant structure includes a substrate and a protrusion disposed on the substrate. The protrusion has a vertical side wall with a rounded corner, a protuberant width and a protuberant length. At least one of the protuberant width and the protuberant length is not greater than 33 nm.

Abstract translation: 提供立方形隆起结构。 立方体隆起结构包括基板和设置在基板上的突起。 突起具有垂直侧壁，其具有圆角，突出宽度和突出长度。 突出宽度和突出长度中的至少一个不大于33nm。

公开(公告)号：US20120286353A1

公开(公告)日：2012-11-15

申请号：US13106852

申请日：2011-05-12

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

Abstract: A trench MOS structure is disclosed. The trench MOS structure includes a substrate, an epitaxial layer, a doping well, a doping region and a trench gate. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. The trench gate is partially disposed in the doping region. The trench gate has a bottle shaped profile with a top section smaller than a bottom section, both are partially disposed in the doping well. The bottom section of two adjacent trench gates results in a higher electrical field around the trench MOS structures.

Abstract translation: 公开了一种沟槽MOS结构。 沟槽MOS结构包括衬底，外延层，掺杂阱，掺杂区和沟槽栅。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 沟槽栅极部分地设置在掺杂区域中。 沟槽门具有瓶形轮廓，其顶部部分小于底部部分，都部分地设置在掺杂井中。 两个相邻沟槽栅极的底部部分导致沟槽MOS结构周围的较高电场。

公开(公告)号：US20120298992A1

公开(公告)日：2012-11-29

申请号：US13117126

申请日：2011-05-26

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L23/544

CPC classification number: H01L22/34

Abstract: A test layout structure includes a substrate, a first oxide region of a first height, a second oxide region of a second height, a plurality of border regions, and a test layout pattern. The first oxide region is disposed on the substrate. The second oxide region is also disposed on the substrate and adjacent to the first oxide region. The first height is substantially different from the second height. A plurality of border regions are disposed between the first oxide region and the second oxide region. The test layout pattern includes a plurality of individual sections. A test region is disposed between two of the adjacent individual sections which are parallel to each other.

Abstract translation: 测试布局结构包括基板，第一高度的第一氧化物区域，第二高度的第二氧化物区域，多个边界区域和测试布局图案。 第一氧化物区域设置在基板上。 第二氧化物区域也设置在衬底上并与第一氧化物区域相邻。 第一高度与第二高度大致不同。 多个边界区域设置在第一氧化物区域和第二氧化物区域之间。 测试布局图案包括多个单独的部分。 测试区域设置在彼此平行的两个相邻的单独部分之间。

公开(公告)号：US20120288683A1

公开(公告)日：2012-11-15

申请号：US13104943

申请日：2011-05-10

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: B32B3/00 ,  B05D5/02

CPC classification number: H01L21/0338 ,  B81B2203/0361 ,  B81B2203/0384 ,  B81C1/00103 ,  H01L21/0337 ,  H01L21/28123 ,  H01L29/42376 ,  Y10T428/24612

Abstract: The protuberant structure of the present invention includes a substrate and a protrusion disposed on the substrate. The protrusion has a top side, a bottom side and a tapered side wall disposed between the top side and the bottom side. The top side has an extremely small top width which is not greater than 32 nm.

Abstract translation: 本发明的突出结构包括基板和设置在基板上的突起。 突起具有设置在顶侧和底侧之间的顶侧，底侧和锥形侧壁。 顶侧具有不大于32nm的非常小的顶部宽度。

公开(公告)号：US20120286352A1

公开(公告)日：2012-11-15

申请号：US13104924

申请日：2011-05-10

Applicant: Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/7813 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66734

Abstract: A trench MOS structure is provided. The trench MOS structure includes a substrate, an epitaxial layer, a trench, a gate isolation, a trench gate, a guard ring and a reinforcement structure within the guard ring. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The trench is disposed in the epitaxial layer. The gate isolation covers the inner wall of the trench. The trench gate is disposed in the trench and has the first conductivity type. The guard ring has a second conductivity type and is disposed within the epitaxial layer. The reinforcement structure has an electrically insulating material and is disposed within the guard ring.

Abstract translation: 提供沟槽MOS结构。 沟槽MOS结构包括保护环内的衬底，外延层，沟槽，栅极隔离，沟槽栅极，保护环和加强结构。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 沟槽设置在外延层中。 栅极隔离覆盖沟槽的内壁。 沟槽栅设置在沟槽中并且具有第一导电类型。 保护环具有第二导电类型并且设置在外延层内。 加强结构具有电绝缘材料并且设置在保护环内。

公开(公告)号：US08963282B2

公开(公告)日：2015-02-24

申请号：US13231961

申请日：2011-09-14

Applicant: Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

Inventor： Tse-Yao Huang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/72 ,  H01L23/31 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/311 ,  H01L21/561 ,  H01L21/76224 ,  H01L21/78 ,  H01L23/3178 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

Abstract translation: 半导体结构包括矩阵，集成电路和划线。 矩阵包括划线区域和电路区域。 集成电路设置在电路区域内。 划痕线设置在划线区域内并且包括设置在矩阵中并且邻近电路区域的裂缝停止沟槽。 裂缝停止沟槽与电路区域的一侧平行，并填充有格栅形式的复合材料以形成裂纹停止结构。