Invention Application
- Patent Title: FINFET SPACER ETCH FOR eSiGe IMPROVEMENT
- Patent Title (中): 用于电子改进的FINFET间隔器
-
Application No.: US13918622Application Date: 2013-06-14
-
Publication No.: US20140367751A1Publication Date: 2014-12-18
- Inventor: Hong YU , Hyucksoo YANG , Puneet KHANNA
- Applicant: GLOBALFOUNDRIES Inc.
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/306 ; H01L29/78

Abstract:
A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.
Public/Granted literature
- US09356147B2 FinFET spacer etch for eSiGe improvement Public/Granted day:2016-05-31
Information query
IPC分类: