公开(公告)号：US20140367751A1

公开(公告)日：2014-12-18

申请号：US13918622

申请日：2013-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong YU ,  Hyucksoo YANG ,  Puneet KHANNA

IPC: H01L21/28 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/66795

Abstract: A method for etching FinFET spacers by inserting a Si recess step directly after the traditional spacer ME step and the resulting device are provided. Embodiments include forming a gate on a substrate having a silicon fin, the gate having a nitride cap on an upper surface thereof and an oxide cap on an upper surface of the nitride cap; forming a dielectric layer over the silicon fin and the gate; removing the dielectric layer from an upper surface of the oxide cap and an upper surface of the silicon fin; recessing the silicon fin; and removing the dielectric layer from side surfaces of the silicon fin and the remaining silicon fin.

Abstract translation: 通过在传统的间隔物ME步骤之后直接插入Si凹陷步骤和所得到的器件来蚀刻FinFET间隔物的方法。 实施例包括在具有硅翅片的基板上形成栅极，栅极在其上表面具有氮化物盖，在氮化物盖的上表面上具有氧化物盖; 在所述硅片和所述栅极上形成介电层; 从所述氧化物盖的上表面和所述硅片的上表面去除所述电介质层; 凹陷硅片; 并且从硅片和剩余的硅片的侧表面去除电介质层。

公开(公告)号：US20140179093A1

公开(公告)日：2014-06-26

申请号：US13721132

申请日：2012-12-20

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Dae-Han CHOI ,  Wontae HWANG ,  Puneet KHANNA

IPC: H01L21/283

CPC classification number: H01L29/66583 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553

Abstract: Gate structures and methods of fabricating gate structures of semiconductor devices are provided. One method includes, for instance: providing a sacrificial layer over a substrate; patterning the sacrificial layer to form a gate opening within the sacrificial layer; providing a gate structure within the gate opening in the sacrificial layer; and removing the sacrificial layer, leaving the gate structure over the substrate. In enhanced aspects, the method includes: forming a reverse sidewall-spacer within the gate opening within the sacrificial layer, and after providing the gate structure, recessing the gate structure within the gate opening, and providing a gate cap within the gate recess in the gate structure.

Abstract translation: 提供了栅极结构和制造半导体器件的栅极结构的方法。 一种方法包括例如：在衬底上提供牺牲层; 图案化牺牲层以在牺牲层内形成栅极开口; 在所述牺牲层中的所述栅极开口内提供栅极结构; 并去除牺牲层，将栅极结构留在衬底上。 在增强的方面，该方法包括：在牺牲层内的栅极开口内形成反向侧壁间隔物，并且在提供栅极结构之后，在栅极开口内凹入栅极结构，并且在栅极凹部内提供栅极盖 门结构。

公开(公告)号：US20150087134A1

公开(公告)日：2015-03-26

申请号：US14032978

申请日：2013-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tsung-Liang CHEN ,  Hsin-Neng TAI ,  Puneet KHANNA ,  Zhenyu HU ,  Huey-Ming WANG

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/31053 ,  H01L21/31055

Abstract: Methods of facilitating isolation region uniformity include: patterning a semiconductor substrate to form at least one isolation opening within the semiconductor substrate, the patterning comprising leaving, at least in part, a protective hard mask above a portion of the semiconductor substrate; providing an insulating material within and over the at least one isolation opening, and planarizing the insulating material to facilitate fabricating an isolation region within the semiconductor substrate; stopping the planarizing on the protective hard mask and exposing at least a portion of the protective hard mask above the portion of the semiconductor substrate; and non-selectively removing a remaining portion of the insulating material over the at least one isolation opening and the exposed protective hard mask above the portion of the semiconductor substrate while leaving the insulating material within the at least one isolation opening and exposing upper surfaces of the semiconductor substrate, to facilitate isolation region uniformity.

Abstract translation: 促进隔离区域均匀性的方法包括：图案化半导体衬底以在半导体衬底内形成至少一个隔离开口，该图案化包括至少部分地保留在半导体衬底的一部分上方的保护性硬掩模; 在所述至少一个隔离开口内和之上提供绝缘材料，以及对所述绝缘材料进行平坦化以便于制造所述半导体衬底内的隔离区域; 停止在保护性硬掩模上的平坦化，并将至少一部分保护性硬掩模暴露在半导体衬底的部分之上; 并且在所述至少一个隔离开口和所述暴露的所述半导体衬底的所述部分之上的所述暴露的保护性硬掩模之外，在所述至少一个隔离开口内留下所述绝缘材料的同时，将所述绝缘材料的剩余部分非选择性地去除， 半导体衬底，方便隔离区均匀。

公开(公告)号：US20150249129A1

公开(公告)日：2015-09-03

申请号：US14716045

申请日：2015-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laegu KANG ,  Vara Govindeswara Reddy VAKADA ,  Michael GANZ ,  Yi QI ,  Puneet KHANNA ,  Sri Charan VEMULA ,  Srikanth SAMAVEDAM

IPC: H01L29/06 ,  H01L29/167 ,  H01L29/10

CPC classification number: H01L29/0692 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66651

Abstract: A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions.

Abstract translation: 提供了在场氧化物和外延生长的硅之间形成具有受控步长的SSRW FET的方法以及所得到的器件。 实施例包括在衬底上提供SiN层，通过SiN层形成第一，第二和第三间隔的场区氧化物的STI区域并进入衬底，通过受控的消光去除每个STI区域的场氧化物的顶部部分，去除 SiN层，在第一和第二STI区域之间的衬底中形成n型区域和在第二和第三STI区域之间的衬底中的p型区域，并且在衬底上在n上外延生长Si基层 型和p型区。

公开(公告)号：US20150129983A1

公开(公告)日：2015-05-14

申请号：US14079757

申请日：2013-11-14

Applicant: Globalfoundries Inc.

Inventor： Hong YU ,  Hyucksoo YANG ,  Bingwu LIU ,  Puneet KHANNA ,  Lun ZHAO

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having extended embedded stress elements. The methods include, for example: providing a gate structure extending over a fin extending above a substrate; using isotropic etching and anisotropic etching to form an extended cavity within the fin, where the extended cavity in part undercuts the gate structure, and where the using of the isotropic etching and the anisotropic etching deepens the extended cavity into the fin below the undercut gate structure; and forming an embedded stress element at least partially within the extended cavity, including below the gate structure.

Abstract translation: 鳍型晶体管制造方法和结构被提供具有延伸的嵌入应力元件。 所述方法包括例如：提供在衬底上延伸的翅片上延伸的栅极结构; 使用各向同性蚀刻和各向异性蚀刻在翅片内形成延伸空腔，其中延伸空腔部分地削弱了栅极结构，并且其中使用各向同性蚀刻和各向异性蚀刻将扩展腔加深到底切栅结构下方的翅片 ; 以及至少部分地在所述延伸空腔内形成嵌入的应力元件，包括在所述栅极结构下方。

公开(公告)号：US20150053981A1

公开(公告)日：2015-02-26

申请号：US14511811

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vara Govindeswara Reddy VAKADA ,  Laegu KANG ,  Michael P. GANZ ,  Yi QI ,  Puneet KHANNA ,  Sri Charan VEMULA ,  Srikanth SAMAVEDAM

IPC: H01L29/167 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L29/167 ,  H01L21/2205 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/088 ,  H01L27/092 ,  H01L29/04 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66651

Abstract: A methodology enabling the formation of steep channel profiles for devices, such as SSRW FETs, having a resultant channel profiles that enables suppression of threshold voltage variation and the resulting device are disclosed. Embodiments include providing STI regions in a silicon wafer; performing a deep well implantation of a dopant into the silicon wafer between STI regions; forming a recess in the doped silicon wafer between the STI regions; performing a shallow well implantation of the dopant into the silicon wafer in the recess; and forming Si:C on the doped silicon wafer in the recess.

Abstract translation: 公开了一种使得能够形成具有能够抑制阈值电压变化的结果信道分布和所得到的器件的诸如SSRW FET的器件的陡峭通道轮廓的方法。 实施例包括在硅晶片中提供STI区域; 在STI区域之间对硅晶片进行深阱注入掺杂剂; 在所述STI区域之间的所述掺杂硅晶片中形成凹部; 在所述凹部中进行所述掺杂剂的浅阱注入到所述硅晶片中; 并在凹陷中的掺杂硅晶片上形成Si：C。