发明申请
- 专利标题： INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE
- 专利标题（中）： 输入/输出存储器映射单元和北桥
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申请号： US14523705申请日： 2014-10-24
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公开(公告)号： US20150120978A1公开(公告)日： 2015-04-30
- 发明人: Vydhyanathan Kalyanasundharam , Philip Ng , Maggie Chan , Vincent Cueva , Liang Chen , Anthony Asaro , Jimshed Mirza , Greggory D. Donley , Bryan Broussard , Benjamin Tsien , Yaniv Adiri
- 申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
- 申请人地址： CA Markham US CA Sunnyvale
- 专利权人： ATI Technologies ULC,Advanced Micro Devices, Inc.
- 当前专利权人： ATI Technologies ULC,Advanced Micro Devices, Inc.
- 当前专利权人地址： CA Markham US CA Sunnyvale
- 主分类号： G06F12/10
- IPC分类号： G06F12/10 ; G06F13/24 ; G06F12/12
摘要：
The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.
公开/授权文献
- US10025721B2 Input/output memory map unit and northbridge 公开/授权日：2018-07-17
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