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    INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE
    3.
    发明申请
    INPUT/OUTPUT MEMORY MAP UNIT AND NORTHBRIDGE 有权
    输入/输出存储器映射单元和北桥

    公开(公告)号：US20150120978A1

    公开(公告)日：2015-04-30

    申请号：US14523705

    申请日：2014-10-24

    申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    发明人： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Maggie Chan ,  Vincent Cueva ,  Liang Chen ,  Anthony Asaro ,  Jimshed Mirza ,  Greggory D. Donley ,  Bryan Broussard ,  Benjamin Tsien ,  Yaniv Adiri

    IPC分类号： G06F12/10 ,  G06F13/24 ,  G06F12/12

    CPC分类号： G06F12/1009 ,  G06F12/1045 ,  G06F12/12 ,  G06F2212/684

    摘要： The present invention provides for page table access and dirty bit management in hardware via a new atomic test[0] and OR and Mask. The present invention also provides for a gasket that enables ACE to CCI translations. This gasket further provides request translation between ACE and CCI, deadlock avoidance for victim and probe collision, ARM barrier handling, and power management interactions. The present invention also provides a solution for ARM victim/probe collision handling which deadlocks the unified northbridge. These solutions includes a dedicated writeback virtual channel, probes for IO requests using 4-hop protocol, and a WrBack Reorder Ability in MCT where victims update older requests with data as they pass the requests.

    摘要翻译： 本发明通过新的原子测试[0]和OR和Mask来提供在硬件中的页表访问和脏位管理。 本发明还提供了一种使ACE能够进行CCI翻译的垫圈。 该垫片进一步提供了ACE和CCI之间的请求转换，针对受害者和探针冲突的死锁避免，ARM屏障处理和电源管理交互。 本发明还提供了一种用于ARM受害者/探测器碰撞处理的解决方案，其使统一的北桥陷入僵局。 这些解决方案包括一个专用的回写虚拟通道，使用4跳协议的IO请求的探测器和MCT中的WrBack重新排序能力，其中受害者通过数据通过请求时更新旧的请求。

    Light-weight memory expansion in a coherent memory system
    9.
    发明授权
    Light-weight memory expansion in a coherent memory system 有权

    公开(公告)号：US11036658B2

    公开(公告)日：2021-06-15

    申请号：US16249649

    申请日：2019-01-16

    申请人： Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    发明人： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Alexander J Branover ,  Kevin M. Lepak

    IPC分类号： G06F13/16 ,  G06F9/38 ,  G06F9/50 ,  G06F9/48

    摘要： Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.