Invention Application
US20150364336A1 UNIFORM GATE HEIGHT FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES
有权
混合型非平面半导体器件的均匀栅极高度
- Patent Title: UNIFORM GATE HEIGHT FOR MIXED-TYPE NON-PLANAR SEMICONDUCTOR DEVICES
- Patent Title (中): 混合型非平面半导体器件的均匀栅极高度
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Application No.: US14306920Application Date: 2014-06-17
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Publication No.: US20150364336A1Publication Date: 2015-12-17
- Inventor: Hong YU , Haigou HUANG , Jin Ping LIU , Huang LIU
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L21/3105
- IPC: H01L21/3105 ; H01L21/311

Abstract:
A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.
Public/Granted literature
- US09230822B1 Uniform gate height for mixed-type non-planar semiconductor devices Public/Granted day:2016-01-05
Information query
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