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    TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF
    1.
    发明申请
    TRANSISTOR STRUCTURES AND FABRICATION METHODS THEREOF 有权
    晶体管结构及其制造方法

    公开(公告)号：US20160126316A1

    公开(公告)日：2016-05-05

    申请号：US14526831

    申请日：2014-10-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xusheng WU ,  Jin Ping LIU ,  Min-hwa CHI

    IPC: H01L29/165 ,  H01L29/737 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L21/02 ,  H01L29/78 ,  H01L29/08

    CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7848

    Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

    Abstract translation: 提供晶体管结构和制造晶体管结构的方法。 所述方法包括：至少部分地在衬底内制造晶体管结构，所述制造包括：在所述衬底内提供空腔; 以及至少部分地在所述空腔内形成所述晶体管结构的第一部分和第二部分，所述第一部分至少部分地设置在所述基板和所述第二部分之间，其中所述第一部分禁止材料从所述第二部分扩散到所述第二部分 基质。 在一个实施例中，晶体管结构是场效应晶体管结构，并且第一部分和第二部分包括场效应晶体管结构的源极区或漏极区之一。 在另一实施例中，晶体管结构是双极结型晶体管结构。

    DEFECT-FREE RELAXED COVERING LAYER ON SEMICONDUCTOR SUBSTRATE WITH LATTICE MISMATCH
    2.
    发明申请
    DEFECT-FREE RELAXED COVERING LAYER ON SEMICONDUCTOR SUBSTRATE WITH LATTICE MISMATCH 有权
    半导体基板上的无缺陷的覆盖层与绝缘错配

    公开(公告)号：US20150295047A1

    公开(公告)日：2015-10-15

    申请号：US14252447

    申请日：2014-04-14

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Haigou HUANG ,  Huang LIU ,  Jin Ping LIU

    IPC: H01L29/165 ,  H01L21/02 ,  H01L29/267 ,  H01L29/06 ,  H01L29/205 ,  H01L21/311 ,  H01L21/306

    CPC classification number: H01L21/02381 ,  H01L21/02439 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111

    Abstract: A defect-free, relaxed semiconductor covering layer (e.g., epitaxial SiGe) over a semiconductor substrate (e.g., Si) is provided having a strain relaxation degree above about 80% and a non-zero threading dislocation density of less than about 100/cm2. A lattice mismatch exists between the substrate and the covering layer. The covering layer also has a non-zero thickness that may be less than about 0.5 microns. The strain relaxation degree and threading dislocation are achieved by exposing defects at or near a surface of an initial semiconductor layer on the substrate (i.e., exposing defects via selective etch and filling-in any voids created), planarizing the filled-in surface, and creating the covering layer (e.g., growing epitaxy) on the planarized, filled-in surface, which is also planarized.

    Abstract translation: 提供半导体衬底（例如Si）上的无缺陷的，松弛的半导体覆盖层（例如，外延SiGe），其具有高于约80％的应变松弛度和小于约100 / cm 2的非零穿透位错密度 。 衬底和覆盖层之间存在晶格失配。 覆盖层还具有可以小于约0.5微米的非零厚度。 应变松弛度和穿透位错是通过在基板上的初始半导体层的表面处或附近暴露缺陷来实现的（即，通过选择性蚀刻暴露缺陷并填充所产生的任何空隙），平坦化填充表面，以及 在平坦化的填充表面上形成覆盖层（例如，生长外延），其也被平坦化。

    FABRICATING FIN STRUCTURES WITH DOPED MIDDLE PORTIONS
    5.
    发明申请
    FABRICATING FIN STRUCTURES WITH DOPED MIDDLE PORTIONS 审中-公开
    使用中间部分制作精细结构

    公开(公告)号：US20160225771A1

    公开(公告)日：2016-08-04

    申请号：US15096389

    申请日：2016-04-12

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xusheng WU ,  Jin Ping LIU

    IPC: H01L27/092 ,  H01L29/06 ,  H01L29/167 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/225

    CPC classification number: H01L27/0924 ,  H01L21/2254 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823892 ,  H01L21/845 ,  H01L27/0922 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/66803

    Abstract: Methods are provided for fabricating fin structures. The methods include: fabricating at least one fin structure, the at least one fin structure having a doped middle portion separating an upper portion from a lower portion, and the fabricating comprising: providing an isolation layer in contact with the lower portion of the at least one fin structure; forming a doping layer above the isolation layer and in contact with the at least one fin structure; and annealing the doping layer to diffuse dopants therefrom into the at least one fin structure to form the doped middle portion thereof, wherein the isolation layer inhibits diffusion of dopants from the doping layer into the lower portion of the at least one fin structure.

    Abstract translation: 提供了用于制造翅片结构的方法。 所述方法包括：制造至少一个翅片结构，所述至少一个翅片结构具有将上部与下部分隔开的掺杂中间部分，并且所述制造包括：提供与所述至少下部的下部接触的隔离层 一个鳍结构; 在所述隔离层上方形成掺杂层并与所述至少一个翅片结构接触; 以及退火所述掺杂层以将掺杂剂从其中扩散到所述至少一个鳍结构中以形成其掺杂的中间部分，其中所述隔离层抑制掺杂剂从所述掺杂层扩散到所述至少一个鳍结构的下部。

    METHODS OF FABRICATING DEFECT-FREE SEMICONDUCTOR STRUCTURES
    9.
    发明申请
    METHODS OF FABRICATING DEFECT-FREE SEMICONDUCTOR STRUCTURES 有权
    制作无缺陷半导体结构的方法

    公开(公告)号：US20150123250A1

    公开(公告)日：2015-05-07

    申请号：US14070823

    申请日：2013-11-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hung-Wei LIU ,  Zhiguo SUN ,  Huang LIU ,  Jin Ping LIU

    IPC: H01L21/311 ,  H01L23/58

    CPC classification number: H01L23/564 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823418 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

    Abstract translation: 提供了有助于制造无缺陷半导体结构的方法，其包括例如：提供介电层，该电介质层包括至少一种可消耗材料; 选择性地去除所述电介质层的一部分，其中所述选择性去除部分地消耗所述至少一种可消耗材料的剩余部分，在所述电介质层的剩余部分内留下耗尽区; 并且对所述介质层的所述耗尽区进行处理处理，以用至少一种替代的可消耗材料恢复所述耗尽区，从而有助于制造无缺陷的半导体结构。

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