Invention Application
- Patent Title: METHOD AND APPARATUS OF MULTI THRESHOLD VOLTAGE CMOS
- Patent Title (中): 多路电压CMOS方法与装置
-
Application No.: US14498180Application Date: 2014-09-26
-
Publication No.: US20160093535A1Publication Date: 2016-03-31
- Inventor: Jeffrey Junhao XU , Choh Fei YEAP
- Applicant: QUALCOMM Incorporated
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L21/28 ; H01L29/161 ; H01L29/51 ; H01L21/02 ; H01L21/3213 ; H01L27/088 ; H01L29/49
Abstract:
A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.
Public/Granted literature
- US09922880B2 Method and apparatus of multi threshold voltage CMOS Public/Granted day:2018-03-20
Information query
IPC分类:
