公开(公告)号：US20160181161A1

公开(公告)日：2016-06-23

申请号：US14581244

申请日：2014-12-23

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Jeffrey Junhao XU ,  Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L21/8234 ,  H01L29/06 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1041 ,  H01L29/66803 ,  H01L29/7851

Abstract: A fin-based structure may include fins on a surface of a semiconductor substrate. Each of the fins may include a doped portion proximate to the surface of the semiconductor substrate. The fin-based structure may also include an isolation layer disposed between the fins and on the surface of the semiconductor substrate. The fin-based structure may also include a recessed isolation liner on sidewalls of the doped portion of the fins. An unlined doped portion of the fins may extend from the recessed isolation liner to an active potion of the fins at a surface of the isolation layer. The isolation layer is disposed on the unlined doped portion of the fins.

Abstract translation: 鳍状结构可以包括半导体衬底的表面上的翅片。 每个翅片可以包括靠近半导体衬底的表面的掺杂部分。 鳍状结构还可以包括设置在散热片之间和半导体衬底的表面上的隔离层。 鳍状结构还可以包括在散热片的掺杂部分的侧壁上的凹陷的隔离衬垫。 翅片的无衬里的掺杂部分可以从凹入的隔离衬垫延伸到隔离层的表面处的翅片的活性部分。 隔离层设置在翅片的无衬里的掺杂部分上。

公开(公告)号：US20160071795A1

公开(公告)日：2016-03-10

申请号：US14483110

申请日：2014-09-10

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG ,  Jeffrey Junhao XU

IPC: H01L23/522 ,  H01L49/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/8234 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/823475 ,  H01L27/0805 ,  H01L28/60 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device capacitor structure within middle of line (MOL) layers includes a first MOL interconnect layer. The first MOL interconnect layer may include active contacts between a set of dummy gate contacts on an active surface of a semiconductor substrate. The device capacitor structure also includes a second MOL interconnect layer. The second MOL interconnect layer may include a set of stacked contacts directly on exposed ones of the active contacts. The second MOL interconnect layer may also include a set of fly-over contacts on portions of an etch-stop layer on some of the active contacts. The fly-over contacts and the stacked contacts may provide terminals of a set of device capacitors.

Abstract translation: 线路（MOL）层中间的器件电容器结构包括第一MOL互连层。 第一MOL互连层可以包括半导体衬底的有源表面上的一组虚拟栅极触点之间的有源触点。 器件电容器结构还包括第二MOL互连层。 第二MOL互连层可以直接在活动触点的暴露的一个上包括一组堆叠的触点。 第二MOL互连层还可以包括在一些有源触点上的蚀刻停止层的部分上的一组飞越触点。 飞越触点和堆叠的触点可以提供一组器件电容器的端子。

公开(公告)号：US20150194525A1

公开(公告)日：2015-07-09

申请号：US14269981

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Vladimir MACHKAOUTSAN ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.

Abstract translation: 形成FinFET器件的半导体鳍片的方法包括在半导体鳍片上共形沉积硅 - 锗（SiGe）的非晶或多晶薄膜。 该方法还包括氧化非晶或多晶薄膜以将锗从非晶或多晶薄膜扩散到半导体鳍中。 这种方法还包括去除非晶或多晶薄膜的氧化部分。

公开(公告)号：US20170033020A1

公开(公告)日：2017-02-02

申请号：US15293213

申请日：2016-10-13

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L21/8238 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract translation: 集成电路（IC）装置可以包括在第一类型区域中的第一类型的第一有源晶体管。 第一有源晶体管可以在第一有源晶体管的有效部分中具有第一类型功函数材料和低通道掺杂剂浓度。 IC器件还可以包括在第一类型区域中的第一类型的第一隔离晶体管。 第二有源晶体管可以具有第二类型功函数材料，并且第一隔离晶体管的有源部分中的低通道掺杂剂浓度。 第一隔离晶体管可以布置成与第一有源晶体管相邻。

公开(公告)号：US20160254261A1

公开(公告)日：2016-09-01

申请号：US14633011

申请日：2015-02-26

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L27/092 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L21/823828 ,  B82Y10/00 ,  H01L21/321 ,  H01L21/32133 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823878 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0642 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785

Abstract: An integrated circuit (IC) device may include a first active transistor of a first-type in a first-type region. The first active transistor may have a first-type work function material and a low channel dopant concentration in an active portion of the first active transistor. The IC device may also include a first isolation transistor of the first-type in the first-type region. The second active transistor may have a second-type work function material and the low channel dopant concentration in an active portion of the first isolation transistor. The first isolation transistor may be arranged adjacent to the first active transistor.

Abstract translation: 集成电路（IC）装置可以包括在第一类型区域中的第一类型的第一有源晶体管。 第一有源晶体管可以在第一有源晶体管的有效部分中具有第一类型功函数材料和低通道掺杂剂浓度。 IC器件还可以包括在第一类型区域中的第一类型的第一隔离晶体管。 第二有源晶体管可以具有第二类型功函数材料，并且第一隔离晶体管的有源部分中的低通道掺杂剂浓度。 第一隔离晶体管可以布置成与第一有源晶体管相邻。

公开(公告)号：US20160148936A1

公开(公告)日：2016-05-26

申请号：US14673485

申请日：2015-03-30

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Vladimir MACHKAOUTSAN ,  Mustafa BADAROGLU ,  Junjing BAO ,  John Jianhong ZHU ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24 ,  H01L29/417 ,  H01L29/08 ,  H01L29/06 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L27/0924 ,  H01L21/285 ,  H01L21/76897 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all surface area of a regrown source/drain region of the semiconductor device proximate to the gate stack.

Abstract translation: 半导体器件包括栅极堆叠。 该半导体器件还包括环绕接触件，布置在靠近栅极堆叠处的半导体器件的再生长源极/漏极区域的基本上所有的表面区域附近。

公开(公告)号：US20150325515A1

公开(公告)日：2015-11-12

申请号：US14274470

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： John Jianhong ZHU ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Kern RIM ,  Zhongze WANG

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/5228 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor interconnects and methods for making semiconductor interconnects. An interconnect may include a first via of a first conductive material between a first conductive interconnect layer and a first middle of line (MOL) interconnect layer. The first MOL interconnect layer is on a first level. The first via is fabricated with a single damascene process. Such a semiconductor interconnect also includes a second via of a second conductive material between the first conductive interconnect layer and a second MOL interconnect layer. The second MOL interconnect layer is on a second level. The second via is fabricated with a dual damascene process. The first conductive material is different than the second conductive material.

Abstract translation: 用于半导体互连的半导体互连和方法。 互连可以包括在第一导电互连层和第一中间线（MOL）互连层之间的第一导电材料的第一通孔。 第一个MOL互连层位于第一层。 第一个通孔用单个镶嵌工艺制造。 这种半导体互连还包括在第一导电互连层和第二MOL互连层之间的第二导电材料的第二通孔。 第二个MOL互连层位于第二层。 第二个通孔用双镶嵌工艺制造。 第一导电材料与第二导电材料不同。

公开(公告)号：US20170104088A1

公开(公告)日：2017-04-13

申请号：US15385811

申请日：2016-12-20

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/225

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

公开(公告)号：US20160093535A1

公开(公告)日：2016-03-31

申请号：US14498180

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/161 ,  H01L29/51 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/517

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

Abstract translation: 分别在第一鳍片和第二鳍片上形成公共结构化叠层的第一和第二实例。 公共结构化堆叠包括功函数金属层和阻挡层。 将公共结构化堆叠的第一实例的阻挡层蚀刻通过，并且共同结构的第一实例的功函数金属层被部分蚀刻。 部分蚀刻形成更薄的功函数金属层，其具有作为功能金属的氧化物作为新的阻挡层。 在新的阻挡层上形成栅极元件。

公开(公告)号：US20160071847A1

公开(公告)日：2016-03-10

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  Matthew Michael NOWAK ,  Choh Fei YEAP ,  Roawen CHEN

IPC: H01L27/088 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。