公开(公告)号：US20180166340A1

公开(公告)日：2018-06-14

申请号：US15880512

申请日：2018-01-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/51 ,  H01L27/088 ,  H01L29/161 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/517

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

公开(公告)号：US20160322391A1

公开(公告)日：2016-11-03

申请号：US15210420

申请日：2016-07-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/20 ,  H01L29/10 ,  H01L29/16

CPC classification number: H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

Abstract: A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

公开(公告)号：US20150249038A1

公开(公告)日：2015-09-03

申请号：US14274099

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  John Jianhong ZHU ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

Abstract translation: 半导体器件包括具有将第一互连层耦合到沟槽的通孔的管芯。 半导体器件还包括在沟槽的侧壁和相邻表面上以及在通孔的侧壁上的阻挡层。 半导体器件在第一互连层的表面上具有掺杂的导电层。 掺杂导电层在通孔的侧壁之间延伸。 半导体器件还包括在通孔和沟槽中的阻挡层上的导电材料。 导电材料位于设置在第一互连层表面上的掺杂导电层上。

公开(公告)号：US20150155364A1

公开(公告)日：2015-06-04

申请号：US14093105

申请日：2013-11-29

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66651 ,  H01L21/28035 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78648 ,  H01L29/78696

Abstract: A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively.

Abstract translation: 完全耗尽的绝缘体上硅MOSFET晶体管，其阈值电压变化较小。 掺杂晶体管的衬底以在掩埋氧化物层下方形成接地层。 在掩埋氧化物层上形成轻掺杂沟道。 在沟道上形成氮氧化硅的栅极电介质，并且在栅极电介质上形成多晶硅栅极。 对于p型掺杂沟道（对于n沟道MOSFET），多晶硅栅极被掺杂以具有不大于4.2电子伏特的功函数，对于n型掺杂沟道（对于p型掺杂沟道），功率不小于5.0电子伏特， 通道MOSFET）。 掩埋氧化物层和沟道的厚度不必分别大于20纳米和10纳米。

公开(公告)号：US20150145070A1

公开(公告)日：2015-05-28

申请号：US14283168

申请日：2014-05-20

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L29/423 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L29/4238 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/823437 ,  H01L27/0207 ,  H01L27/0886

Abstract: Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length.

Abstract translation: 在模具上制造器件的方法以及管芯上的器件。 一种方法可以包括图案化第一区域以产生具有第一栅极长度的第一栅极和具有第一工艺的第一接触多晶硅间距（CPP）。 第一个CPP小于单一图案光刻极限。 该方法还包括图案化第一区域以产生具有第二栅极长度的第二栅极或具有第二工艺的第二CPP。 第二CPP小于单模光刻极限。 第二栅极长度不同于第一栅极长度。

公开(公告)号：US20150145069A1

公开(公告)日：2015-05-28

申请号：US14269828

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L21/324 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/66803 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0603 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin.

Abstract translation: 在翅片场效应晶体管（FinFET）中制造鳍片的方法包括曝光耦合到FinFET衬底的单晶鳍结构。 单晶鳍结构是第一种材料。 该方法还包括在第一温度下将第二材料注入到暴露的单晶鳍结构中。 第一个温度降低了单晶翅片结构的非晶化。 植入的单晶鳍结构包括至少20％的第一材料。 该方法还包括在第二温度下退火植入的翅片结构。 第二温度降低植入翅片结构中的晶体缺陷以形成翅片。

公开(公告)号：US20170104088A1

公开(公告)日：2017-04-13

申请号：US15385811

申请日：2016-12-20

Applicant: QUALCOMM Incorporated

Inventor： Vladimir MACHKAOUTSAN ,  Jeffrey Junhao XU ,  Stanley Seungchul SONG ,  Mustafa BADAROGLU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/225

CPC classification number: H01L29/66803 ,  H01L21/2254 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A portion of a bulk silicon (Si) is formed into a fin, having a fin base and, on the fin base, an in-process fin. The fin base is doped Si and the in-process fin is silicon germanium (SiGe). The in-process SiGe fin has a source region and a drain region. Boron is in-situ doped into the drain region and into the source region. Optionally, boron is in-situ doped by forming an epi-layer, having boron, on the drain region and on the source region, and drive-in annealing to diffuse boron in the source region and the drain region.

公开(公告)号：US20160133634A1

公开(公告)日：2016-05-12

申请号：US14995195

申请日：2016-01-13

Applicant: QUALCOMM INCORPORATED

Inventor： Niladri Narayan MOJUMDER ,  Stanley Seungchul SONG ,  Zhongze WANG ,  Choh Fei YEAP

IPC: H01L27/11 ,  H01L29/423 ,  H01L27/105

CPC classification number: H01L27/1052 ,  G11C11/412 ,  H01L27/1104 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/785

Abstract: A complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cell. A CMOS SRAM cell in accordance with an aspect of the present disclosure includes a bit line and a word line. Such a CMOS SRAM memory cell further includes a CMOS memory cell having at least a first p-channel device comprising a first channel material that differs from a substrate material of the CMOS memory cell, the first channel material having an intrinsic channel mobility greater than the intrinsic channel mobility of the substrate material, the first p-channel device coupling the CMOS memory cell to the bit line and the word line.

公开(公告)号：US20160093535A1

公开(公告)日：2016-03-31

申请号：US14498180

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/161 ,  H01L29/51 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/517

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

Abstract translation: 分别在第一鳍片和第二鳍片上形成公共结构化叠层的第一和第二实例。 公共结构化堆叠包括功函数金属层和阻挡层。 将公共结构化堆叠的第一实例的阻挡层蚀刻通过，并且共同结构的第一实例的功函数金属层被部分蚀刻。 部分蚀刻形成更薄的功函数金属层，其具有作为功能金属的氧化物作为新的阻挡层。 在新的阻挡层上形成栅极元件。

公开(公告)号：US20160071847A1

公开(公告)日：2016-03-10

申请号：US14480156

申请日：2014-09-08

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  Matthew Michael NOWAK ,  Choh Fei YEAP ,  Roawen CHEN

IPC: H01L27/088 ,  G06F17/50

CPC classification number: H01L27/0886 ,  G03F7/00 ,  G06F17/5068 ,  H01L21/823431 ,  H01L27/0207

Abstract: A method for half-node scaling a circuit layout in accordance with an aspect of the present disclosure includes vertical devices on a die. The method includes reducing a fin pitch and a gate pitch of the vertical devices on the die. The method also includes scaling a wavelength to define at least one reduced area geometric pattern of the circuit layout.

Abstract translation: 根据本公开的一个方面的用于半节点缩放电路布局的方法包括裸片上的垂直设备。 该方法包括降低管芯上的垂直装置的翅片间距和栅极间距。 该方法还包括缩放波长以限定电路布局的至少一个缩小区域几何图案。