Invention Application
US20160204781A1 SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
审中-公开
用于在电路中引导路径延迟变化的系统和方法，并生成容错位
- Patent Title: SYSTEMS AND METHODS FOR LEVERAGING PATH DELAY VARIATIONS IN A CIRCUIT AND GENERATING ERROR-TOLERANT BITSTRINGS
- Patent Title (中): 用于在电路中引导路径延迟变化的系统和方法，并生成容错位
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Application No.: US14913454Application Date: 2014-08-28
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Publication No.: US20160204781A1Publication Date: 2016-07-14
- Inventor: James Plusquellic , James Aarestad
- Applicant: STC.UNM
- International Application: PCT/US14/53276 WO 20140828
- Main IPC: H03K19/003
- IPC: H03K19/003 ; H03K19/21
Abstract:
A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
Public/Granted literature
Information query
