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公开(公告)号:US11132178B2
公开(公告)日:2021-09-28
申请号:US16856887
申请日:2020-04-23
申请人: STC.UNM
发明人: James Plusquellic
摘要: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
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公开(公告)号:US10956557B2
公开(公告)日:2021-03-23
申请号:US16067757
申请日:2017-01-11
申请人: STC.UNM
发明人: James Plusquellic , Wenjie Che , Dylan Ismari
IPC分类号: G06F21/44 , G06F21/70 , G06F21/30 , G06F21/73 , H04L9/08 , H04L9/32 , H04L9/06 , G06F7/58 , G06F21/34
摘要: An authentication protocol using a Hardware-Embedded Delay PUF (“HELP”), which derives randomness from within-die path delay variations that occur along the paths within a hardware implementation of a cryptographic primitive, for example, the Advanced Encryption Standard (“AES”) algorithm or Secure Hash Algorithm 3 (“SHA-3”). The digitized timing values which represent the path delays are stored in a database on a secure server (verifier) as an alternative to storing PUF response bitstrings thereby enabling the development of an efficient authentication protocol that provides both privacy and mutual authentication.
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公开(公告)号:US20200293288A1
公开(公告)日:2020-09-17
申请号:US16856887
申请日:2020-04-23
申请人: STC.UNM
发明人: James Plusquellic
摘要: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
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4.
公开(公告)号:US20200235735A1
公开(公告)日:2020-07-23
申请号:US16843660
申请日:2020-04-08
申请人: STC.UNM
发明人: James Plusquellic , James Aarestad
摘要: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
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5.
公开(公告)号:US20190089355A1
公开(公告)日:2019-03-21
申请号:US16185921
申请日:2018-11-09
申请人: STC.UNM
发明人: James Plusquellic , James Aarestad
摘要: A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.
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公开(公告)号:US20180349100A1
公开(公告)日:2018-12-06
申请号:US16051427
申请日:2018-07-31
申请人: STC.UNM
发明人: James Plusquellic
CPC分类号: G06F7/588 , G06F2207/58 , G09C1/00 , H04L9/002 , H04L9/0866 , H04L2209/12 , H04L2209/26 , Y04S40/24
摘要: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
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公开(公告)号:US10048939B2
公开(公告)日:2018-08-14
申请号:US14907423
申请日:2014-08-28
申请人: STC.UNM
发明人: James Plusquellic
摘要: This disclosure describes techniques for analyzing statistical quality of bitstrings produced by a physical unclonable function (PUF). The PUF leverages resistance variations in the power grid wires of an integrated circuit. Temperature and voltage stability of the bitstrings are analyzed. The disclosure also describes converting a voltage drop into a digital code, wherein the conversion is resilient to simple and differential side-channel attacks.
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公开(公告)号:US11863304B2
公开(公告)日:2024-01-02
申请号:US16759729
申请日:2018-10-30
申请人: STC.UNM
发明人: James Plusquellic
CPC分类号: H04L9/003 , H04L9/0631 , H04L9/16 , H04L2209/12
摘要: A side-channel attack countermeasure that leverages implementation diversity and dynamic partial reconfiguration as mechanisms to reduce correlation in the power traces measured during a differential power analysis (DPA) attack. The technique changes the underlying hardware implementation of any encryption algorithm using dynamic partial reconfiguration (DPR) to resist side-channel-based attacks.
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公开(公告)号:US11095461B2
公开(公告)日:2021-08-17
申请号:US16346772
申请日:2017-11-03
申请人: STC.UNM
发明人: James Plusquellic , Wenjie Che
摘要: The Distribution Effect is proposed for the HELP PUF that is based on purposely introducing biases in the mean and range parameters of path delay distributions to enhance entropy. The biased distributions are then used in the bitstring construction process to introduce differences in the bit values associated with path delays that would normally remain fixed. Offsets are computed to fine tune a token's digitized path delays as a means of maximizing entropy and reproducibility in the generated bitstrings: a first population-based offset method computes median values using data from multiple tokens (i.e., the population) and a second chip-specific technique is proposed which fine tunes path delays using enrollment data from the authenticating token.
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公开(公告)号:US10366253B2
公开(公告)日:2019-07-30
申请号:US15534116
申请日:2015-12-15
申请人: STC.UNM
发明人: James Plusquellic
摘要: A Hardware-Embedded Delay Physical Unclonable Function (“HELP PUF”) leverages entropy by monitoring path stability and measuring path delays from core logic macros. Reliability and security enhancing techniques for the HELP PUF reduce bit flip errors during regeneration of the bitstring across environmental variations and improve cryptographic strength along with the corresponding difficulty of carrying out model building attacks. A voltage-based enrollment process screens unstable paths on normally synthesized (glitchy) functional units and reduces bit flip errors by carrying out enrollment at multiple supply voltages controlled using on-chip voltage regulators.
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