发明申请
US20160343846A1 (110) Surface Orientation for Reducing Fermi-Level-Pinning Between High-K Dielectric and Group Iii-V Compound Semiconductor Device
审中-公开
（110）用于降低高K电介质和组Iii-V复合半导体器件之间的费米能级引线的表面取向
- 专利标题： (110) Surface Orientation for Reducing Fermi-Level-Pinning Between High-K Dielectric and Group Iii-V Compound Semiconductor Device
- 专利标题（中）： （110）用于降低高K电介质和组Iii-V复合半导体器件之间的费米能级引线的表面取向
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申请号： US15225298申请日： 2016-08-01
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公开(公告)号： US20160343846A1公开(公告)日： 2016-11-24
- 发明人: Chao-Ching Cheng , Chih-Hsin Ko , Hsingien Wann
- 申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L29/04 ; H01L29/20 ; H01L21/308 ; H01L29/51 ; H01L29/66 ; H01L29/06 ; H01L29/49 ; H01L21/28 ; H01L29/45
摘要：
A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.
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