公开(公告)号：US20250081622A1

公开(公告)日：2025-03-06

申请号：US18531089

申请日：2023-12-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Tsung-En Lee ,  Jer-Fu Wang ,  Chao-Ching Cheng ,  Iuliana Radu ,  Cheng-Chi Chuang ,  Chih-Sheng Chang ,  Ching-Wei Tsai

IPC: H01L27/06 ,  H01L21/8258

Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

公开(公告)号：US12199169B2

公开(公告)日：2025-01-14

申请号：US17154110

申请日：2021-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  Shao-Ming Yu ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L29/66 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a plurality of nanostructures over a substrate, and a gate electrode surrounding the nanostructures. The semiconductor device structure includes a source/drain portion adjacent to the gate electrode, and a semiconductor layer between the gate electrode and the source/drain portion.

公开(公告)号：US12165729B2

公开(公告)日：2024-12-10

申请号：US17856328

申请日：2022-07-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Hung-Li Chiang ,  Yu-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen

IPC: G11C5/06 ,  G11C11/16 ,  G11C11/22 ,  H10B51/20 ,  H10B51/30 ,  H10B51/40 ,  H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/85 ,  H10N70/00 ,  H10N70/20

Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.

公开(公告)号：US20240315152A1

公开(公告)日：2024-09-19

申请号：US18669541

申请日：2024-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Jer-Fu Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen

IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

CPC classification number: H10N70/8413 ,  H10B63/20 ,  H10N70/011 ,  H10N70/231 ,  H10N70/826

Abstract: A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.

公开(公告)号：US12062696B2

公开(公告)日：2024-08-13

申请号：US18352249

申请日：2023-07-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yi-Tse Hung ,  Ang-Sheng Chou ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  Chao-Ching Cheng

IPC: H01L29/78 ,  H01L23/36 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/1033 ,  H01L23/36 ,  H01L29/0607 ,  H01L29/0669 ,  H01L29/66477 ,  H01L29/78

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

公开(公告)号：US20240260279A1

公开(公告)日：2024-08-01

申请号：US18610689

申请日：2024-03-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Yu-Sheng Chen

IPC: H10B63/00 ,  G11C13/00 ,  H10N70/00

CPC classification number: H10B63/80 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H10B63/20 ,  H10N70/011 ,  G11C2013/0045 ,  G11C2013/0078

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. One or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. The plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. The first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. The first memory stack is closer to the second memory stack than the third memory stack.

公开(公告)号：US20240250122A1

公开(公告)日：2024-07-25

申请号：US18624386

申请日：2024-04-02

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li CHIANG ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages

公开(公告)号：US10672667B2

公开(公告)日：2020-06-02

申请号：US16417341

申请日：2019-05-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Chen-Feng Hsu ,  Yu-Lin Yang ,  Tung Ying Lee ,  Chih Chieh Yeh

IPC: H01L29/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/775 ,  H01L29/08 ,  H01L21/8234 ,  B82Y10/00

Abstract: Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

公开(公告)号：US20200075756A1

公开(公告)日：2020-03-05

申请号：US16678045

申请日：2019-11-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chao-Ching Cheng ,  Chih-Hsin Ko ,  Hsingien Wann

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/06 ,  H01L21/308 ,  H01L21/28 ,  H01L29/20 ,  H01L29/04 ,  H01L29/66 ,  H01L29/51 ,  H01L29/45

Abstract: A device with improved device performance, and method of manufacturing the same, are disclosed. An exemplary device includes a group III-V compound semiconductor substrate that includes a surface having a (110) crystallographic orientation, and a gate stack disposed over the group III-V compound semiconductor substrate. The gate stack includes a high-k dielectric layer disposed on the surface having the (110) crystallographic orientation, and a gate electrode disposed over the high-k dielectric layer.

公开(公告)号：US10522622B2

公开(公告)日：2019-12-31

申请号：US15979123

申请日：2018-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chao-Ching Cheng ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Shih-Syuan Huang ,  Hung-Li Chiang

IPC: H01L29/76 ,  H01L31/113 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234

Abstract: A multi-gate semiconductor structure includes a plurality of nanowires, a gate structure disposed over the plurality of nanowires, and source/drain structures at two ends of each of the plurality of nanowires. The source/drain structures include a conductor, and a bottom surface of the conductor is lower than the plurality of nanowires.