Invention Application
- Patent Title: DETERMINING MULTI-PATTERNING STEP OVERLAY ERROR
- Patent Title (中): 确定多模式步骤覆盖错误
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Application No.: US15170881Application Date: 2016-06-01
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Publication No.: US20160377425A1Publication Date: 2016-12-29
- Inventor: Ajay Gupta , Thanh Huy Ha , Olivier Moreau , Kumar Raja
- Applicant: KLA-Tencor Corporation
- Main IPC: G01B15/00
- IPC: G01B15/00 ; H01J37/22 ; G01B11/27 ; H01L21/67 ; H01L21/68

Abstract:
Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.
Public/Granted literature
- US10062543B2 Determining multi-patterning step overlay error Public/Granted day:2018-08-28
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