Invention Application
US20160377425A1 DETERMINING MULTI-PATTERNING STEP OVERLAY ERROR 审中-公开
确定多模式步骤覆盖错误

DETERMINING MULTI-PATTERNING STEP OVERLAY ERROR
Abstract:
Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.
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