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    Computer assisted weak pattern detection and quantification system
    1.
    发明授权
    Computer assisted weak pattern detection and quantification system 有权

    公开(公告)号：US10740888B2

    公开(公告)日：2020-08-11

    申请号：US15275726

    申请日：2016-09-26

    Applicant: KLA-Tencor Corporation

    Inventor： Naoshin Haque ,  Allen Park ,  Ajay Gupta

    IPC: G06T7/00 ,  H01L21/66

    Abstract: Methods and systems for providing weak pattern (or hotspot) detection and quantification are disclosed. A weak pattern detection and quantification system may include a wafer inspection tool configured to inspect a wafer and detect defects present on the wafer. The system may also include at least one processor in communication with the wafer inspection tool. The at least one processor may be configured to: perform pattern grouping on the detected defects based on design of the wafer; identify regions of interest based on the pattern grouping; identify weak patterns contained in the identified regions of interest, the weak patterns being patterns deviating from the design by an amount greater than a threshold; validate the identified weak patterns; and report the validated weak patterns or facilitate revision of the design of the wafer based on the validated weak patterns.

    Self directed metrology and pattern classification
    2.
    发明授权
    Self directed metrology and pattern classification 有权

    公开(公告)号：US10483081B2

    公开(公告)日：2019-11-19

    申请号：US15247774

    申请日：2016-08-25

    Applicant: KLA-Tencor Corporation

    Inventor： Allen Park ,  Ajay Gupta ,  Jan Lauber

    IPC: H01J37/22 ,  G06K9/62 ,  G06T7/00 ,  G03F7/20 ,  G06T7/11 ,  G01N21/956 ,  G01N21/88 ,  H01L21/66

    Abstract: Methods and systems for determining parameter(s) of a process to be performed on a specimen are provided. One system includes one or more computer subsystems configured for determining an area of a defect detected on a specimen. The computer subsystem(s) are also configured for correlating the area of the defect with information for a design for the specimen and determining a spatial relationship between the area of the defect and the information for the design based on results of the correlating. In addition, the computer subsystem(s) are configured for automatically generating a region of interest to be measured during a process performed for the specimen with a measurement subsystem based on the spatial relationship.

    Automated Pattern Fidelity Measurement Plan Generation
    3.
    发明申请
    Automated Pattern Fidelity Measurement Plan Generation 审中-公开

    公开(公告)号：US20190204237A1

    公开(公告)日：2019-07-04

    申请号：US16296132

    申请日：2019-03-07

    Applicant: KLA-Tencor Corporation

    Inventor： Brian Duffy ,  Ajay Gupta ,  Thanh Huy Ha

    IPC: G01N21/88 ,  G01N23/00 ,  G03F7/20 ,  G01N21/95

    Abstract: Methods and systems for determining parameter(s) of a metrology process to be performed on a specimen are provided. One system includes one or more computer subsystems configured for automatically generating regions of interest (Rats) to be measured during a metrology process performed for the specimen with the measurement subsystem based on a design for the specimen. The computer subsystem(s) are also configured for automatically determining parameter(s) of measurement(s) performed in first and second subsets of the ROIs during the metrology process with the measurement subsystem based on portions of the design for the specimen located in the first and second subsets of the ROIs, respectively. The parameter(s) of the measurement(s) performed in the first subset are determined separately and independently of the parameter(s) of the measurement(s) performed in the second subset.

    Automated pattern fidelity measurement plan generation
    5.
    发明授权
    Automated pattern fidelity measurement plan generation 有权

    公开(公告)号：US10267746B2

    公开(公告)日：2019-04-23

    申请号：US14918394

    申请日：2015-10-20

    Applicant: KLA-Tencor Corporation

    Inventor： Brian Duffy ,  Ajay Gupta ,  Thanh Huy Ha

    IPC: G01N21/88 ,  G01N23/00 ,  G01N21/95 ,  G03F7/20 ,  G01N21/956

    Abstract: Methods and systems for determining parameter(s) of a metrology process to be performed on a specimen are provided. One system includes one or more computer subsystems configured for automatically generating regions of interest (ROIs) to be measured during a metrology process performed for the specimen with the measurement subsystem based on a design for the specimen. The computer subsystem(s) are also configured for automatically determining parameter(s) of measurement(s) performed in first and second subsets of the ROIs during the metrology process with the measurement subsystem based on portions of the design for the specimen located in the first and second subsets of the ROIs, respectively. The parameter(s) of the measurement(s) performed in the first subset are determined separately and independently of the parameter(s) of the measurement(s) performed in the second subset.

    Automated Pattern Fidelity Measurement Plan Generation
    6.
    发明申请
    Automated Pattern Fidelity Measurement Plan Generation 审中-公开
    自动图案保真度测量计划生成

    公开(公告)号：US20160116420A1

    公开(公告)日：2016-04-28

    申请号：US14918394

    申请日：2015-10-20

    Applicant: KLA-Tencor Corporation

    Inventor： Brian Duffy ,  Ajay Gupta ,  Thanh Huy Ha

    IPC: G01N21/88 ,  G01N23/00 ,  G01N21/95

    CPC classification number: G01N21/8851 ,  G01N21/9501 ,  G01N21/956 ,  G01N23/00 ,  G01N2021/8883 ,  G03F7/70625

    Abstract: Methods and systems for determining parameter(s) of a metrology process to be performed on a specimen are provided. One system includes one or more computer subsystems configured for automatically generating regions of interest (ROIs) to be measured during a metrology process performed for the specimen with the measurement subsystem based on a design for the specimen. The computer subsystem(s) are also configured for automatically determining parameter(s) of measurement(s) performed in first and second subsets of the ROIs during the metrology process with the measurement subsystem based on portions of the design for the specimen located in the first and second subsets of the ROIs, respectively. The parameter(s) of the measurement(s) performed in the first subset are determined separately and independently of the parameter(s) of the measurement(s) performed in the second subset.

    Abstract translation: 提供了用于确定要在样本上执行的计量过程的参数的方法和系统。 一个系统包括一个或多个计算机子系统，其被配置为在基于样本的设计的测量子系统为样本执行的度量过程期间自动生成要测量的感兴趣区域（ROI）。 计算机子系统还被配置为在测量子系统的计量过程中自动确定在ROI的第一和第二子集中执行的测量参数，其基于位于 ROI的第一和第二子集。 在第一子集中执行的测量的参数被分开地和独立于在第二子集中执行的测量的参数来确定。

    DETERMINING MULTI-PATTERNING STEP OVERLAY ERROR
    7.
    发明申请
    DETERMINING MULTI-PATTERNING STEP OVERLAY ERROR 审中-公开
    确定多模式步骤覆盖错误

    公开(公告)号：US20160377425A1

    公开(公告)日：2016-12-29

    申请号：US15170881

    申请日：2016-06-01

    Applicant: KLA-Tencor Corporation

    Inventor： Ajay Gupta ,  Thanh Huy Ha ,  Olivier Moreau ,  Kumar Raja

    IPC: G01B15/00 ,  H01J37/22 ,  G01B11/27 ,  H01L21/67 ,  H01L21/68

    CPC classification number: H01J37/222 ,  G03F7/70633 ,  H01J2237/221 ,  H01J2237/24578 ,  H01J2237/31798

    Abstract: Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.

    Abstract translation: 提供了用于在多图案化步骤过程中确定印刷在晶片上的设计的不同图案特征之间确定覆盖误差的方法和系统。 对于多图案化步骤设计，将第一图案化步骤的设计用作参考，并且对于每个剩余的图案化步骤的设计被合成移位，直到合成移位的设计基于全局图像步骤与整个图像具有最佳的全局对准， 设计对齐。 相对于第一图案化步骤的设计，每个图案化步骤的每个设计的最终合成位移提供了使用多图案化技术印刷在晶片上的任何两个特征之间的相对重叠误差的测量。

    Self Directed Metrology and Pattern Classification
    8.
    发明申请
    Self Directed Metrology and Pattern Classification 审中-公开
    自导计量和模式分类

    公开(公告)号：US20160372303A1

    公开(公告)日：2016-12-22

    申请号：US15247774

    申请日：2016-08-25

    Applicant: KLA-Tencor Corporation

    Inventor： Allen Park ,  Ajay Gupta ,  Jan Lauber

    IPC: H01J37/22 ,  G06K9/62 ,  G06T7/00

    CPC classification number: H01J37/222 ,  G01N21/956 ,  G01N2021/8883 ,  G03F7/70625 ,  G06K9/6267 ,  G06T7/0004 ,  G06T7/11 ,  G06T2207/30148 ,  H01J2237/2817 ,  H01L22/12 ,  H01L22/20

    Abstract: Methods and systems for determining parameter(s) of a process to be performed on a specimen are provided. One system includes one or more computer subsystems configured for determining an area of a defect detected on a specimen. The computer subsystem(s) are also configured for correlating the area of the defect with information for a design for the specimen and determining a spatial relationship between the area of the defect and the information for the design based on results of the correlating. In addition, the computer subsystem(s) are configured for automatically generating a region of interest to be measured during a process performed for the specimen with a measurement subsystem based on the spatial relationship.

    Abstract translation: 提供了用于确定要在样本上执行的过程的参数的方法和系统。 一个系统包括被配置用于确定在样本上检测到的缺陷区域的一个或多个计算机子系统。 计算机子系统还被配置为将缺陷的区域与用于样本的设计的信息相关联，并且基于相关的结果确定缺陷的区域与设计的信息之间的空间关系。 此外，计算机子系统被配置为在基于空间关系的测量子系统对于具有样本的处理过程中自动生成要测量的感兴趣区域。

    Semiconductor inspection and metrology systems for distributing job among the CPUs or GPUs based on logical image processing boundaries
    10.
    发明授权
    Semiconductor inspection and metrology systems for distributing job among the CPUs or GPUs based on logical image processing boundaries 有权

    公开(公告)号：US11237872B2

    公开(公告)日：2022-02-01

    申请号：US15978626

    申请日：2018-05-14

    Applicant: KLA-TENCOR CORPORATION

    Inventor： Ajay Gupta ,  Sankar Venkataraman ,  Sashi Balasingam ,  Mohan Mahadevan

    IPC: G06F9/50 ,  G06F9/48

    Abstract: Real-time job distribution software architectures for high bandwidth, hybrid processor computation systems for semiconductor inspection and metrology are disclosed. The imaging processing computer architecture can be scalable by changing the number of CPUs and GPUs to meet computing needs. The architecture is defined using a master node and one or more worker nodes to run image processing jobs in parallel for maximum throughput. The master node can receive input image data from a semiconductor wafer or reticle. Jobs based on the input image data are distributed to one of the worker nodes. Each worker node can include at least one CPU and at least one GPU. The image processing job can contain multiple tasks, and each of the tasks can be assigned to one of the CPU or GPU in the worker node using a worker job manager to process the image.

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