公开(公告)号：US10062543B2

公开(公告)日：2018-08-28

申请号：US15170881

申请日：2016-06-01

Applicant: KLA-Tencor Corporation

Inventor： Ajay Gupta ,  Thanh Huy Ha ,  Olivier Moreau ,  Kumar Raja

IPC: G06K9/00 ,  H01L21/76 ,  G01B11/00 ,  H01L23/544 ,  G06F19/00 ,  H01J37/22 ,  G03F7/20

CPC classification number: H01J37/222 ,  G03F7/70633 ,  H01J2237/221 ,  H01J2237/24578 ,  H01J2237/31798

Abstract: Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.

公开(公告)号：US20160377425A1

公开(公告)日：2016-12-29

申请号：US15170881

申请日：2016-06-01

Applicant: KLA-Tencor Corporation

Inventor： Ajay Gupta ,  Thanh Huy Ha ,  Olivier Moreau ,  Kumar Raja

IPC: G01B15/00 ,  H01J37/22 ,  G01B11/27 ,  H01L21/67 ,  H01L21/68

CPC classification number: H01J37/222 ,  G03F7/70633 ,  H01J2237/221 ,  H01J2237/24578 ,  H01J2237/31798

Abstract: Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.

Abstract translation: 提供了用于在多图案化步骤过程中确定印刷在晶片上的设计的不同图案特征之间确定覆盖误差的方法和系统。 对于多图案化步骤设计，将第一图案化步骤的设计用作参考，并且对于每个剩余的图案化步骤的设计被合成移位，直到合成移位的设计基于全局图像步骤与整个图像具有最佳的全局对准， 设计对齐。 相对于第一图案化步骤的设计，每个图案化步骤的每个设计的最终合成位移提供了使用多图案化技术印刷在晶片上的任何两个特征之间的相对重叠误差的测量。