A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.