- 专利标题: IN-MEMORY INTERCONNECT PROTOCOL CONFIGURATION REGISTERS
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申请号: US14928981申请日: 2015-10-30
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公开(公告)号: US20170123987A1公开(公告)日: 2017-05-04
- 发明人: Kevin Y. Cheng , David A. Roberts
- 申请人: Advanced Micro Devices, Inc.
- 主分类号: G06F12/08
- IPC分类号: G06F12/08 ; G06F13/42
摘要:
Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.
公开/授权文献
- US09767028B2 In-memory interconnect protocol configuration registers 公开/授权日:2017-09-19