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公开(公告)号：US12099789B2
公开(公告)日：2024-09-24
申请号：US17118442
申请日：2020-12-10
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin Y. Cheng , Sooraj Puthoor , Onur Kayiran
IPC: G06F30/331 , G06F9/38 , G06F30/34
CPC classification number: G06F30/331 , G06F9/3877 , G06F30/34
Abstract: Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.
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公开(公告)号：US20240111355A1
公开(公告)日：2024-04-04
申请号：US17956606
申请日：2022-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Sergey Blagodurov , Kevin Y. Cheng , SeyedMohammad SeyedzadehDelcheh , Masab Ahmad
IPC: G06F1/329
CPC classification number: G06F1/329
Abstract: Methods and systems are disclosed for reducing power consumption by a system including a digital unit and an optical unit. Techniques disclosed comprise generating a workload signature of an incoming workload to be executed by the system. Based on the generated workload signature, techniques disclosed comprise matching the incoming workload with a profile of stored workload profiles. The workload profiles are generated by a trace capture unit. Based on the associated profile, a task submission transaction is sent to the optical unit of the system, representative of a request to execute the incoming workload by the optical unit.
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公开(公告)号：US10540200B2
公开(公告)日：2020-01-21
申请号：US15809940
申请日：2017-11-10
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin Y. Cheng , David A. Roberts , William C. Brantley
Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.
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公开(公告)号：US20220188493A1
公开(公告)日：2022-06-16
申请号：US17118442
申请日：2020-12-10
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin Y. Cheng , Sooraj Puthoor , Onur Kayiran
IPC: G06F30/331 , G06F30/34 , G06F9/38
Abstract: Methods, devices, and systems for information communication. Information transmitted from a host to a graphics processing unit (GPU) is received by information analysis circuitry of a field-programmable gate array (FPGA). A pattern in the information is determined by the information analysis circuitry. A predicted information pattern is determined, by the information analysis circuitry, based on the information. An indication of the predicted information pattern is transmitted to the host. Responsive to a signal from the host based on the predicted information pattern, the FPGA is reprogrammed to implement decompression circuitry based on the predicted information pattern. In some implementations, the information includes a plurality of packets. In some implementations, the predicted information pattern includes a pattern in a plurality of packets. In some implementations, the predicted information pattern includes a zero data pattern.
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Patent Agency Ranking
公开(公告)号：US09767028B2
公开(公告)日：2017-09-19
申请号：US14928981
申请日：2015-10-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin Y. Cheng , David A. Roberts
IPC: G06F12/00 , G06F12/0862 , G06F13/42
CPC classification number: G06F12/0862 , G06F9/4401 , G06F13/42 , G06F15/7821 , G06F2212/1024 , G06F2212/45
Abstract: Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.
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公开(公告)号：US20170048358A1
公开(公告)日：2017-02-16
申请号：US15138485
申请日：2016-04-26
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Roberts , Kevin Y. Cheng , Nathan Hu
IPC: H04L29/06 , H04L12/741
Abstract: Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.
Abstract translation: 考虑了用于减少节点间带宽的系统，装置和方法。 计算机系统包括请求节点向目标节点发送事务。 请求节点发送包含寄存器标识符（ID）的数据包，代替数据包中的数据值。 寄存器ID表示存储数据值的目标节点中的寄存器。 寄存器ID在数据包中使用的数据比数据值少。 数据值可以是引用目标节点中的存储器位置的存储器地址。 所接收的分组还可以包括指示针对目标数据值执行的操作的操作码。
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公开(公告)号：US20190146829A1
公开(公告)日：2019-05-16
申请号：US15809940
申请日：2017-11-10
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin Y. Cheng , David A. Roberts , William C. Brantley
Abstract: A hardware context manager in a field-programmable gate array (FPGA) device includes configuration logic configured to program one or more programming regions in the FPGA device based on configuration data for implementing a target configuration of the one or more programming regions. Context management logic in the hardware context manager is coupled with the configuration logic and saves a first context corresponding to the target configuration by retrieving first state information from the set of one or more programming regions, where the first state information is generated based on the target configuration, and storing the retrieved first state information in a context memory. The context management logic restores the first context by transferring the first state information from the context memory to the one or more programming regions, and causing the configuration logic to program the one or more programming regions based on the configuration data.
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公开(公告)号：US10079916B2
公开(公告)日：2018-09-18
申请号：US15138485
申请日：2016-04-26
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Roberts , Kevin Y. Cheng , Nathan Hu
IPC: H04L29/06 , G06F9/00 , G06F13/00 , H04L12/741
Abstract: Systems, apparatuses, and methods for reducing inter-node bandwidth are contemplated. A computer system includes requesting nodes sending transactions to target nodes. A requesting node sends a packet that includes a register identifier (ID) in place of a data value in the packet. The register ID indicates a register in the target node storing the data value. The register ID uses fewer bits in the packet than the data value. The data value may be a memory address referencing a memory location in the target node. The received packet may also include an opcode indicating an operation to perform on the targeted data value.
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公开(公告)号：US20170123987A1
公开(公告)日：2017-05-04
申请号：US14928981
申请日：2015-10-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin Y. Cheng , David A. Roberts
CPC classification number: G06F12/0862 , G06F9/4401 , G06F13/42 , G06F15/7821 , G06F2212/1024 , G06F2212/45
Abstract: Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used for storing the interconnect protocol configuration registers may also be made cacheable to reduce the latency of accesses to the interconnect protocol configuration registers. Interconnect protocol configuration registers which are used during a startup routine may be prefetched into the host's cache to make the startup routine more efficient. The interconnect protocol configuration registers for various interconnect protocols may include one or more of device capability tables, memory-side statistics (e.g., to support two-level memory data mapping decisions), advanced memory and interconnect features such as repair resources and routing tables, prefetching hints, error correcting code (ECC) bits, lists of device capabilities, set and store base address, capability, device ID, status, configuration, capabilities, and other settings.
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