A direct memory access (DMA) system is implemented in an electronic device that communicates with a host device via a communication bus, and includes an available descriptor notification circuit and a DMA controller. The available descriptor notification circuit indicates whether at least one valid descriptor is available in the host device. The available descriptor notification circuit is set by at least the host device. The at least one valid descriptor records DMA data transfer control information. The DMA controller fetches the at least one valid descriptor from the host device when the available descriptor notification circuit indicates that the at least one valid descriptor is available in the host device, and refers to the at least one valid descriptor fetched from the host device to perform a DMA data transfer between the electronic device and the host device.