Abstract:
Universal Serial Bus (USB) devices supporting super speed and non-super speed connections for communication with a host device includes a plurality of endpoints (EPs), a non-super speed connection port, a super speed connection port and a configuration unit. The non-super speed connection port and the super speed connection port are connected to the host device. The configuration unit is arranged for dividing the EPs to first and second groups of EPs according to a bandwidth requirement, determining whether a super speed connection with the host device is successfully established and configuring the first group of EPs to operate at a super speed and configuring the second group of EPs to operate at a non-super speed when the super speed connection with the host device is successfully established such that the USB device communicates with the host device at both the super speed and the non-super speed.
Abstract:
Universal Serial Bus (USB) devices supporting super speed and non-super speed connections for communication with a host device includes a plurality of endpoints (EPs), a non-super speed connection port, a super speed connection port and a configuration unit. The non-super speed connection port and the super speed connection port are connected to the host device. The configuration unit is arranged for dividing the EPs to first and second groups of EPs according to a bandwidth requirement, determining whether a super speed connection with the host device is successfully established and configuring the first group of EPs to operate at a super speed and configuring the second group of EPs to operate at a non-super speed when the super speed connection with the host device is successfully established such that the USB device communicates with the host device at both the super speed and the non-super speed.
Abstract:
A direct memory access (DMA) system is implemented in an electronic device that communicates with a host device via a communication bus, and includes an available descriptor notification circuit and a DMA controller. The available descriptor notification circuit indicates whether at least one valid descriptor is available in the host device. The available descriptor notification circuit is set by at least the host device. The at least one valid descriptor records DMA data transfer control information. The DMA controller fetches the at least one valid descriptor from the host device when the available descriptor notification circuit indicates that the at least one valid descriptor is available in the host device, and refers to the at least one valid descriptor fetched from the host device to perform a DMA data transfer between the electronic device and the host device.