Invention Application
- Patent Title: Semiconductor Constructions, Patterning Methods, and Methods of Forming Electrically Conductive Lines
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Application No.: US15685907Application Date: 2017-08-24
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Publication No.: US20170352616A1Publication Date: 2017-12-07
- Inventor: Vishal Sipani , Kyle Armstrong , Michael D. Hyatt , Michael Dean Van Patten , David A. Kewley , Ming-Chuan Yang
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Main IPC: H01L23/525
- IPC: H01L23/525 ; H01L23/532 ; H01L23/528 ; H01L21/033 ; H01L21/768

Abstract:
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.
Public/Granted literature
- US10217706B2 Semiconductor constructions Public/Granted day:2019-02-26
Information query
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