公开(公告)号：US10741445B2

公开(公告)日：2020-08-11

申请号：US16520445

申请日：2019-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler G. Hansen ,  Ming-Chuan Yang ,  Vishal Sipani

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522 ,  H01L23/535 ,  H01L23/532

Abstract: Integrated circuits include a first conductive structure at a first level of the integrated circuit, a second conductive structure at a second level of the integrated circuit, a first conductor at a third level of the integrated circuit between the first level and the second level, a second conductor at the third level and parallel to the first conductor, and a third conductor at the third level and parallel to the first conductor and to the second conductor. The first conductive structure is in physical and electrical contact with the first conductor and the second conductor. The second conductive structure is in physical and electrical contact with the second conductor and the third conductor.

公开(公告)号：US09972532B2

公开(公告)日：2018-05-15

申请号：US14887359

申请日：2015-10-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tyler G. Hansen ,  Ming-Chuan Yang ,  Vishal Sipani

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/033 ,  H01L21/311 ,  H01L23/535 ,  H01L23/532

CPC classification number: H01L21/76895 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass.

公开(公告)号：US08969214B2

公开(公告)日：2015-03-03

申请号：US13893546

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： Scott L. Light ,  Kyle Armstrong ,  Michael D. Hyatt ,  Vishal Sipani

IPC: H01L21/302 ,  H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337

Abstract: A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are formed on opposing sides of the first features. After forming the sidewall spacers, spaced second features derived from a second lithographic patterning step are formed. At least some of individual of the second features are laterally between and laterally spaced from immediately adjacent of the first features in at least one straight-line vertical cross-section that passes through the first and second features. After the second lithographic patterning step, all of only some of the sidewall spacers in said at least one cross-section is removed.

Abstract translation: 在衬底上形成图案的方法包括形成从第一平版印刷图案化步骤导出的间隔开的第一特征。 侧壁间隔件形成在第一特征的相对侧上。 在形成侧壁间隔物之后，形成从第二平版印刷图案化步骤得到的隔开的第二特征。 第二特征中的至少一些个体在穿过第一和第二特征的至少一个直线垂直横截面中在第一特征之间横向间隔开并且横向间隔开。 在第二平版印刷图案化步骤之后，所有至少一个横截面中的所有侧壁间隔物都被去除。

公开(公告)号：US08530352B2

公开(公告)日：2013-09-10

申请号：US13769473

申请日：2013-02-18

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Baosuo Zhou ,  Ming-Chuan Yang

IPC: H01L21/44

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines.

Abstract translation: 一些实施例包括形成开口的方法。 例如，结构可以具有多条导电线上的材料。 可以在材料上方形成多个环形特征，其中环形特征与线交叉。 图案化掩模可以形成在环形特征上，其中图案化掩模留下通过图案化掩模中的窗口暴露的环形特征的段。 环形特征的暴露部分可以限定多个开口，并且这样的开口可以被转移到材料中以形成延伸到导电线的开口。

公开(公告)号：US20150099362A1

公开(公告)日：2015-04-09

申请号：US14049135

申请日：2013-10-08

Applicant: Micron Technology, Inc.

Inventor： Scott L. Light ,  Vishal Sipani ,  Michael D. Hyatt

IPC: H01L21/308

CPC classification number: H01L21/0337

Abstract: A method including forming a line pattern in a substrate includes using a plurality of longitudinally spaced projecting features formed along respective guide lines as a template in forming a plurality of directed self-assembled (DSA) lines that individually comprise at least one of (a): the spaced projecting features and DSA material longitudinally there-between, and (b): are laterally between and laterally spaced from immediately adjacent of the guide lines. Substrate material elevationally inward of and laterally between the DSA lines may be processed using the DSA lines as a mask.

Abstract translation: 包括在衬底中形成线图案的方法包括在形成多个定向自组装（DSA）线时使用沿着相应引导线形成的多个纵向间隔开的突出特征作为模板，所述定向自组装（DSA）线分别包括以下中的至少一个：（a） ：在其间纵向延伸的间隔开的突出特征和DSA材料，和（b）之间：在紧邻引导线之间横向间隔开并且横向间隔开。 可以使用DSA线作为掩模来处理DSA线之间和横向上的基底材料。

公开(公告)号：US08946086B2

公开(公告)日：2015-02-03

申请号：US14160659

申请日：2014-01-22

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/266 ,  H01L27/105

CPC classification number: H01L21/76805 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/266 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/3205 ,  H01L21/76802 ,  H01L27/1052 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming a pattern. First lines are formed over a first material, and second lines are formed over the first lines. The first and second lines form a crosshatch pattern. The first openings are extended through the first material. Portions of the first lines that are not covered by the second lines are removed to pattern the first lines into segments. The second lines are removed to uncover the segments. Masking material is formed between the segments. The segments are removed to form second openings that extend through the masking material to the first material. The second openings are extended through the first material. The masking material is removed to leave a patterned mask comprising the first material having the first and second openings therein. In some embodiments, spacers may be formed along the first and second lines to narrow the openings in the crosshatch pattern.

Abstract translation: 一些实施例包括形成图案的方法。 第一线形成在第一材料上，并且第二线形成在第一线上。 第一行和第二行形成交叉影线图案。 第一开口延伸穿过第一材料。 第一行未覆盖的第一行的部分被删除，以将第一行划分成段。 删除第二行以发现段。 在片段之间形成遮蔽材料。 去除这些段以形成延伸穿过掩模材料到第一材料的第二开口。 第二开口延伸穿过第一材料。 去除掩模材料以留下包含其中具有第一和第二开口的第一材料的图案化掩模。 在一些实施例中，可以沿着第一和第二线形成间隔物以使交叉阴影图案中的开口变窄。

公开(公告)号：US20140342563A1

公开(公告)日：2014-11-20

申请号：US13893546

申请日：2013-05-14

Applicant: Micron Technology, Inc.

Inventor： Scott L. Light ,  Kyle Armstrong ,  Michael D. Hyatt ,  Vishal Sipani

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337

Abstract: A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are formed on opposing sides of the first features. After forming the sidewall spacers, spaced second features derived from a second lithographic patterning step are formed. At least some of individual of the second features are laterally between and laterally spaced from immediately adjacent of the first features in at least one straight-line vertical cross-section that passes through the first and second features. After the second lithographic patterning step, all of only some of the sidewall spacers in said at least one cross-section is removed.

Abstract translation: 在衬底上形成图案的方法包括形成从第一平版印刷图案化步骤导出的间隔开的第一特征。 侧壁间隔件形成在第一特征的相对侧上。 在形成侧壁间隔物之后，形成从第二平版印刷图案化步骤得到的隔开的第二特征。 第二特征中的至少一些个体在穿过第一和第二特征的至少一个直线垂直横截面中在第一特征之间横向间隔开并且横向间隔开。 在第二平版印刷图案化步骤之后，所有至少一个横截面中的所有侧壁间隔物都被去除。

公开(公告)号：US08846517B2

公开(公告)日：2014-09-30

申请号：US14133962

申请日：2013-12-19

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Anton J. deVilliers

IPC: H01L21/3205 ,  H01L21/311 ,  H01L21/033

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338

Abstract: A method of forming a pattern on a substrate includes forming longitudinally elongated first lines and first sidewall spacers longitudinally along opposite sides of the first lines elevationally over an underlying substrate. Longitudinally elongated second lines and second sidewall spacers are formed longitudinally along opposite sides of the second lines. The second lines and the second sidewall spacers cross elevationally over the first lines and the first sidewall spacers. The second sidewall spacers are removed from crossing over the first lines. The first and second lines are removed in forming a pattern comprising portions of the first and second sidewall spacers over the underlying substrate. Other methods are disclosed.

Abstract translation: 在衬底上形成图案的方法包括沿纵向延伸的第一线和第一侧壁隔离件纵向地沿着第一线的相对侧纵向地形成在下面的衬底上。 纵向细长的第二线和第二侧壁间隔物沿着第二线的相对侧纵向地形成。 第二线和第二侧壁间隔物跨越第一线和第一侧壁间隔物横向交叉。 第二侧壁隔离物从第一线上的交叉排出。 第一和第二线在形成包括第一和第二侧壁隔板的部分的图案的基底上移除。 公开了其他方法。

公开(公告)号：US10217706B2

公开(公告)日：2019-02-26

申请号：US15685907

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Kyle Armstrong ,  Michael D. Hyatt ,  Michael Dean Van Patten ,  David A. Kewley ,  Ming-Chuan Yang

IPC: H01L23/525 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.

公开(公告)号：US20170352616A1

公开(公告)日：2017-12-07

申请号：US15685907

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Vishal Sipani ,  Kyle Armstrong ,  Michael D. Hyatt ,  Michael Dean Van Patten ,  David A. Kewley ,  Ming-Chuan Yang

IPC: H01L23/525 ,  H01L23/532 ,  H01L23/528 ,  H01L21/033 ,  H01L21/768

CPC classification number: H01L23/525 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the photoresist features having a narrowed region. The photoresist features are trimmed, which punches through the narrowed region to form a gap. Spacers are formed along sidewalls of the photoresist features. Two of the spacers merge within the gap. The photoresist features are removed to leave a pattern comprising the spacers. The pattern is extended into the substrate to form a plurality of recesses within the substrate. Electrically conductive material is formed within the recesses to create the electrically conductive lines. Some embodiments include semiconductor constructions having a plurality of lines over a semiconductor substrate. Two of the lines are adjacent to one another and are substantially parallel to one another except in a region wherein said two of the lines merge into one another.