发明申请
- 专利标题: MICROELECTRONIC SUBSTRATES HAVING COPPER ALLOY CONDUCTIVE ROUTE STRUCTURES
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申请号: US15674184申请日: 2017-08-10
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公开(公告)号: US20170362684A1公开(公告)日: 2017-12-21
- 发明人: Robert A. May , Sri Ranga Sai Boyapati , Amruthavalli P. Alur , Daniel N. Sobieski
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 主分类号: C22C9/00
- IPC分类号: C22C9/00 ; H01L23/498 ; H01L23/12 ; H01L23/49
摘要:
Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.
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