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    Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate
    1.
    发明授权
    Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate 有权

    公开(公告)号：US11581271B2

    公开(公告)日：2023-02-14

    申请号：US16353164

    申请日：2019-03-14

    申请人： Intel Corporation

    发明人： Rahul Jain ,  Kyu-Oh Lee ,  Islam A. Salama ,  Amruthavalli P. Alur ,  Wei-Lun K. Jen ,  Yongki Min ,  Sheng C. Li

    IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/538

    摘要： Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

    MULTI-LAYER EMBEDDED MAGNETIC INDUCTOR COIL
    6.
    发明申请
    MULTI-LAYER EMBEDDED MAGNETIC INDUCTOR COIL 审中-公开

    公开(公告)号：US20200066627A1

    公开(公告)日：2020-02-27

    申请号：US16108953

    申请日：2018-08-22

    申请人： INTEL CORPORATION

    发明人： Huong Do ,  Kaladhar Radhakrishnan ,  Krishna Bharath ,  Yikang Deng ,  Amruthavalli P. Alur

    IPC分类号： H01L23/498 ,  H01F17/00 ,  H01L21/48 ,  H01L23/522 ,  H01L23/58 ,  H01L49/02 ,  H01L23/64

    摘要： A microelectronics package comprises a substrate that comprises a dielectric and at least two conductor layers within the dielectric, and an inductor structure having a magnetic core at least partially within the dielectric and extending at least between a first conductor layer and a second conductor layer. The inductor structure comprises at least one conductor that extends horizontally at least partially within the magnetic core. The conductor extends in the z-direction within the magnetic core between the first conductor layer and the second conductor layer. One or more vias extend within the dielectric adjacent to the magnetic core between the first conductor layer and the second conductor layer. The conductor of the inductor has a length extending through the magnetic core that is greater than a width of the conductor.

    Substrate patch reconstitution options
    8.
    发明授权
    Substrate patch reconstitution options 有权

    公开(公告)号：US11552019B2

    公开(公告)日：2023-01-10

    申请号：US16299415

    申请日：2019-03-12

    申请人： Intel Corporation

    发明人： Haifa Hariri ,  Amruthavalli P. Alur ,  Wei-Lun K. Jen ,  Islam A. Salama

    IPC分类号： H01L23/538 ,  H01L23/31

    摘要： Embodiments include semiconductor packages. A semiconductor package includes a first patch and a second patch on an interposer. The semiconductor package also includes a first substrate in the first patch, and a second substrate in the second patch. The semiconductor package further includes an encapsulation layer over and around the first and second patches, a plurality of build-up layers on the first patch, the second patch, and the encapsulation layer, and a plurality of dies and a bridge on the build-up layers. The bridge may be communicatively coupled with the first substrate of the first patch and the second substrate of the second patch. The bridge may be an embedded multi-die interconnect bridge (EMIB). The first and second substrates may be EMIBs and/or high-density packaging (HDP) substrates. The bridge may be positioned between two dies, and over an edge of the first patch and an edge of the second patch.