Invention Application
- Patent Title: Interface Circuits Configured to Interface with Multi-Rank Memory
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Application No.: US15584356Application Date: 2017-05-02
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Publication No.: US20180018092A1Publication Date: 2018-01-18
- Inventor: Kwanyeob Chae , Yoonjee Nam , Ji Hun Oh , Shinyoung Yi , Jong-Ryun Choi
- Applicant: Samsung Electronics Co., Ltd.
- Priority: KR10-2016-0088684 20160713
- Main IPC: G06F3/06
- IPC: G06F3/06 ; G11C8/12 ; G11C7/10 ; G06F13/40 ; G06F12/02 ; G06F13/16 ; G11C5/04
Abstract:
An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.
Public/Granted literature
- US09857973B1 Interface circuits configured to interface with multi-rank memory Public/Granted day:2018-01-02
Information query
