公开(公告)号：US09857973B1

公开(公告)日：2018-01-02

申请号：US15584356

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C8/12 ,  G06F13/40 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US20180018092A1

公开(公告)日：2018-01-18

申请号：US15584356

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C8/12 ,  G11C7/10 ,  G06F13/40 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US10073619B2

公开(公告)日：2018-09-11

申请号：US15842295

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G06F13/40 ,  G11C5/04 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.