公开(公告)号：US10756059B2

公开(公告)日：2020-08-25

申请号：US16157642

申请日：2018-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob Chae ,  Sanghoon Joo ,  Jong-Ryun Choi ,  Jin-Ho Choi

IPC: H01L25/065 ,  H01L23/50 ,  H01L23/58 ,  H01L23/60 ,  H01L23/00 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.

公开(公告)号：US09857973B1

公开(公告)日：2018-01-02

申请号：US15584356

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C8/12 ,  G06F13/40 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US10073619B2

公开(公告)日：2018-09-11

申请号：US15842295

申请日：2017-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C7/10 ,  G11C8/12 ,  G06F13/40 ,  G11C5/04 ,  G06F13/16 ,  G06F12/02

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028 ,  Y02D10/14 ,  Y02D10/151

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.

公开(公告)号：US11381231B2

公开(公告)日：2022-07-05

申请号：US16989074

申请日：2020-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob Chae ,  Jong-Ryun Choi

IPC: H03K5/156 ,  H03K5/133 ,  G01R31/317 ,  H03K5/135

Abstract: A digital measurement circuit includes a first input flip-flop which receives a first signal through a data input terminal, receives a first clock signal through a clock input terminal, and outputs a second signal; a second input flip-flop which receives the second signal through a data input terminal, receives a second clock signal, which is an inverted signal of the first clock signal, through a clock input terminal, and outputs a third signal; and a delay line which receives the second signal and outputs first through n-th output signals, wherein n is an integer greater than one, and the first through n-th output signals are sampled based on the third signal to output first through n-th sampling signals is provided.

公开(公告)号：US10977412B2

公开(公告)日：2021-04-13

申请号：US16164055

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-Yeob Chae ,  Jong-Ryun Choi

IPC: G06F17/50 ,  G06F30/394 ,  G06F30/35 ,  G06F30/392

Abstract: To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

公开(公告)号：US09859880B2

公开(公告)日：2018-01-02

申请号：US15290076

申请日：2016-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwan-Yeob Chae ,  Sang-Hoon Joo ,  Sang-Hune Park ,  Jong-Ryun Choi ,  Hoon-Koo Lee

IPC: H03K5/13 ,  H03K19/20 ,  H03K5/134 ,  H03K5/00

CPC classification number: H03K5/13 ,  H03K5/134 ,  H03K19/20 ,  H03K2005/00032

Abstract: A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.

公开(公告)号：US08766691B2

公开(公告)日：2014-07-01

申请号：US13835824

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Ryun Choi ,  Ji-Hun Oh ,  Choong-Bin Lim

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal.

Abstract translation: 占空比误差累积电路包括第一至第n延迟单元和反馈单元。 第一至第n延迟单元分别接收时钟信号，第一输入信号和第二输入信号，以通过基于逻辑电平延迟从第一和第二输入信号选择的一个信号来产生第一输出信号和第二输出信号 的时钟信号。 反馈单元基于第（k + 1）个延迟单元的第二输出信号向第k个延迟单元提供第二输入信号。 第k延迟单元的第一输出信号作为第一输入信号提供给第（k + 1）个延迟单元，并且时钟信号作为第一输入信号提供给第一延迟单元，并作为第二输入提供给第n延迟单元 信号。 占空比误差累积电路有效地校正时钟信号的占空比。

公开(公告)号：US20190197214A1

公开(公告)日：2019-06-27

申请号：US16164055

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan-Yeob Chae ,  Jong-Ryun Choi

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5059 ,  G06F17/5072

Abstract: To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

公开(公告)号：US10115706B2

公开(公告)日：2018-10-30

申请号：US15277339

申请日：2016-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwanyeob Chae ,  Sanghoon Joo ,  Jong-Ryun Choi ,  Jin-Ho Choi

IPC: H01L23/58 ,  H01L25/065 ,  H01L23/50 ,  H01L23/60 ,  H01L23/00

Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.

公开(公告)号：US20180018092A1

公开(公告)日：2018-01-18

申请号：US15584356

申请日：2017-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanyeob Chae ,  Yoonjee Nam ,  Ji Hun Oh ,  Shinyoung Yi ,  Jong-Ryun Choi

IPC: G06F3/06 ,  G11C8/12 ,  G11C7/10 ,  G06F13/40 ,  G06F12/02 ,  G06F13/16 ,  G11C5/04

CPC classification number: G06F3/0601 ,  G06F3/0683 ,  G06F12/0238 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/4072 ,  G11C5/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C8/12 ,  G11C29/023 ,  G11C29/028

Abstract: An interface circuit may include a first FIFO circuit and a second FIFO circuit. The first FIFO circuit may generate first output data based on a first sampling signal and a second sampling signal. The second FIFO circuit may generate second output data based on a third sampling signal and a fourth sampling signal. The first FIFO circuit and the second FIFO circuit may be cross-reset.