A resistance change memory including a memory cell having a resistance change element; a reference voltage generating circuit which generates a reference adjustment voltage; a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor. The reference voltage generating circuit includes a second transistor having a gate coupled to a gate of the first transistor, the reference adjustment voltage changing in accordance with a temperature, and the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in a current value in accordance with the reference adjustment voltage.