公开(公告)号：US20180033475A1

公开(公告)日：2018-02-01

申请号：US15727053

申请日：2017-10-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Katsuyuki FUJITA

IPC: G11C11/16 ,  G11C7/04 ,  G11C13/00

CPC classification number: G11C11/1673 ,  G11C7/04 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2013/0054

Abstract: A resistance change memory including a memory cell having a resistance change element; a reference voltage generating circuit which generates a reference adjustment voltage; a first transistor which has a source and a drain, the drain providing a reference current in accordance with the reference adjustment voltage; and a sense amplifier which compares a cell current flowing through the memory cell with the reference current flowing through the first transistor. The reference voltage generating circuit includes a second transistor having a gate coupled to a gate of the first transistor, the reference adjustment voltage changing in accordance with a temperature, and the first transistor is an n-channel MOS transistor, and operates in a linear region which changes in a current value in accordance with the reference adjustment voltage.

公开(公告)号：US20180277171A1

公开(公告)日：2018-09-27

申请号：US15909502

申请日：2018-03-01

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA ,  Katsuyuki FUJITA

IPC: G11C5/14 ,  G11C11/34

CPC classification number: G11C5/14 ,  G11C5/025 ,  G11C5/063 ,  G11C7/02 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/1697 ,  G11C11/34 ,  G11C27/024 ,  G11C2207/105

Abstract: A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.

公开(公告)号：US20200251153A1

公开(公告)日：2020-08-06

申请号：US16854394

申请日：2020-04-21

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Fumiyoshi MATSUOKA ,  Katsuyuki FUJITA

IPC: G11C5/14 ,  G11C5/02 ,  G11C11/16 ,  G11C7/02 ,  G11C5/06 ,  G11C11/34

Abstract: A semiconductor memory device includes a power source pad, a first bank including a plurality of memory cells, a second bank including a plurality of memory cells, the first bank being sandwiched between the power source pad and the second bank, first power supply lines connected to the power source pad and supplying power to the first bank and not to the second bank, and second power supply lines connected to the power source pad, passing over the first bank, and supplying power to the second bank and not to the first bank.

公开(公告)号：US20180197592A1

公开(公告)日：2018-07-12

申请号：US15913407

申请日：2018-03-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Akira KATAYAMA ,  Katsuyuki FUJITA

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1675 ,  G11C11/2253 ,  G11C11/2273 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/002

Abstract: According to one embodiment, a memory includes a bit line connected to a memory cell; and a read circuit to execute reading of data from the memory cell. The read circuit includes a first circuit having a first input terminal and detecting an output signal from the memory cell; a first transistor to control a current supplied to the memory cell based on a first control signal; and a second transistor. One terminal of the first transistor is connected to the first input terminal, the other terminal of the first transistor is connected to one terminal of the second transistor, the other terminal of the second transistor is connected to the bit line, and the one terminal and the other terminal of the first transistor are charged before data is read from the memory cell.

公开(公告)号：US20180182442A1

公开(公告)日：2018-06-28

申请号：US15903999

申请日：2018-02-23

Applicant: TOSHIBA MEMORY CORPORATION ,  SK HYNIX INC.

Inventor： Katsuyuki FUJITA ,  Hyuck Sang YIM

IPC: G11C11/16 ,  G11C5/14 ,  G11C13/00 ,  G11C11/4076 ,  G11C11/4094 ,  G11C7/04 ,  G11C7/12 ,  G05F1/56

CPC classification number: G11C11/1673 ,  G05F1/56 ,  G11C5/147 ,  G11C7/04 ,  G11C7/12 ,  G11C11/1697 ,  G11C11/4076 ,  G11C11/4094 ,  G11C13/0038 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2207/002

Abstract: According to one embodiment, a semiconductor memory device comprises a first bank and a second bank. Each of the first bank and the second bank comprises a memory cell having a variable resistor element, a reference cell, a sense amplifier having a first input terminal electrically coupled to the memory cell and a second input terminal electrically coupled to the reference cell, and a first transistor electrically coupling the memory cell and the first input terminal of the sense amplifier. A gate of the first transistor of the first hank and a gate of the first transistor of the second bank are independently supplied with a voltage.