Invention Application
- Patent Title: 3D IC BUMP HEIGHT METROLOGY APC
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Application No.: US15831806Application Date: 2017-12-05
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Publication No.: US20180096872A1Publication Date: 2018-04-05
- Inventor: Nai-Han Cheng , Chi-Ming Yang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L21/67
- IPC: H01L21/67 ; G01B11/16 ; G01B11/24 ; H01L21/66 ; G01B11/14 ; H01L25/00 ; H01L25/065 ; H01L23/00 ; H01L21/768

Abstract:
In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One or more substrate warpage parameters of the substrate are measured and an initial position of a lens within a substrate metrology module is calculated based upon the one or more substrate warpage parameters. The lens is then moved to the initial position, and a height and a width of the bump are measured using the substrate metrology module after moving the lens to the initial position.
Public/Granted literature
- US10181415B2 3D IC bump height metrology APC Public/Granted day:2019-01-15
Information query
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