Invention Application
- Patent Title: METHOD TO REDUCE RESISTANCE FOR A COPPER (CU) INTERCONNECT LANDING ON MULTILAYERED METAL CONTACTS, AND SEMICONDUCTOR STRUCTURES FORMED THEREFROM
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Application No.: US15820602Application Date: 2017-11-22
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Publication No.: US20180096933A1Publication Date: 2018-04-05
- Inventor: Jim Shih-Chun Liang , Atsushi Ogino , Justin C. Long
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY GRAND CAYMAN
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY GRAND CAYMAN
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L21/768 ; H01L23/532 ; H01L23/522 ; H01L21/311 ; H01L23/485

Abstract:
A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.
Public/Granted literature
Information query
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