公开(公告)号：US10796973B2

公开(公告)日：2020-10-06

申请号：US16425387

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mankyu Yang ,  Vara Govindeswara Reddy Vakada ,  Edward Maciejewski ,  Brian Greene ,  Atsushi Ogino ,  Vikrant Chauhan ,  Prianka Sengupta

IPC: H01L29/423 ,  H01L21/66 ,  G01R31/26 ,  H01L23/528 ,  H01L23/522

Abstract: Structures for testing a field effect-transistor or Kelvin field-effect transistor, and methods of forming a structure for testing a field-effect transistor or Kelvin field-effect transistor. The structure includes a device-under-testing that has one or more source/drain regions and a first metallization level arranged over the device-under-testing. The first metallization level includes one or more first interconnect lines. The structure further includes a contact level having one or more first contacts arranged between the first metallization level and the device-under-testing. The one or more first contacts directly connect the one or more first interconnect lines with the one or more source/drain regions. The structure further includes a second metallization level arranged over the first metallization level. The second metallization level has a first test pad and one or more second interconnect lines connecting the one or more first interconnect lines with the first test pad.

公开(公告)号：US10147783B2

公开(公告)日：2018-12-04

申请号：US15463465

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino ,  Vikrant Chauhan ,  Kong Boon Yeap ,  Ahmed Hassan

IPC: H01L49/02

Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

公开(公告)号：US20180096933A1

公开(公告)日：2018-04-05

申请号：US15820602

申请日：2017-11-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jim Shih-Chun Liang ,  Atsushi Ogino ,  Justin C. Long

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/311 ,  H01L23/485

CPC classification number: H01L23/5283 ,  H01L21/31144 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/7688 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238

Abstract: A method of forming a semiconductor structure includes forming a first insulating layer containing a first metal layer embedded therein and on a surface of a semiconductor substrate. The method further includes forming an inter-layer dielectric (ILD) layer on the first insulating layer, and forming at least one via trench structure including a first metallization trench and a via in the ILD layer. In addition, the method also includes depositing a metal material to form a first metallization layer in the first metallization trench, a via contact in the via, and a second metal layer on top of at least a portion of the first metal layer in the opening of the first insulating layer. The first metal layer and the second metal layer constitute a multilayer metal contact located in the opening of the first insulating layer.

公开(公告)号：US09899324B1

公开(公告)日：2018-02-20

申请号：US15362499

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shafaat Ahmed ,  Sadanand Vinayak Despande ,  Atsushi Ogino

IPC: H01L23/528 ,  H01L23/544 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76879 ,  H01L23/53238 ,  H01L23/562 ,  H01L23/585 ,  H01L2223/5446

Abstract: A method includes providing a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, and forming a metallic structure on the semiconductor substrate to serve as a bus bar for the printed circuits and/or semiconductor devices. A semiconductor structure is realized with the method, the semiconductor structure including a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, a metallic structure on the semiconductor substrate serving as a bus bar for the printed circuits and/or semiconductor devices, and printed circuits and/or semiconductor devices in the semiconductor areas.

公开(公告)号：US09793216B2

公开(公告)日：2017-10-17

申请号：US15006426

申请日：2016-01-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Joyeeta Nag ,  Jim Shih-Chun Liang ,  Domingo A. Ferrer Luppi ,  Atsushi Ogino ,  Andrew H. Simon ,  Michael P. Chudzik

IPC: H01L23/48 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266

Abstract: Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method according to embodiments of the present disclosure can include: providing a structure including a via including a bulk semiconductor material therein, wherein the via further includes a cavity extending from a top surface of the via to an interior surface of the via, and wherein a portion of the bulk semiconductor material defines at least one sidewall of the cavity; forming a first metal level on the via, wherein the first metal level includes a contact opening positioned over the cavity of the via; forming a metal plug within the cavity to the surface of the via, such that the metal plug conformally contacts a sidewall of the cavity and the interior surface of the via, wherein the metal plug is laterally distal to an exterior sidewall of the via; and forming a contact within the contact opening of the first metal level.

公开(公告)号：US20170062355A1

公开(公告)日：2017-03-02

申请号：US14837737

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jim S. Liang ,  Atsushi Ogino ,  Stephen E. Greco ,  Roger A. Quon

IPC: H01L23/00 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/562 ,  H01L21/31144 ,  H01L23/522 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53257 ,  H01L23/53295

Abstract: A first aspect of the disclosure provides for an integrated circuit structure. The integrated circuit structure may comprise a first metal structure in a first dielectric layer on a substrate in a crack stop area; and a first crack stop structure in a second dielectric layer, the first crack stop structure being over the first metal structure and including: a first metal fill contacting the first metal structure; and an air seam substantially separating the first metal fill and the second dielectric layer.

Abstract translation: 本公开的第一方面提供一种集成电路结构。 集成电路结构可以包括在裂纹停止区域中的衬底上的第一介电层中的第一金属结构; 以及在第二电介质层中的第一裂纹阻挡结构，所述第一裂纹阻挡结构在所述第一金属结构之上，并且包括：与所述第一金属结构接触的第一金属填充物; 以及基本分离第一金属填充物和第二介电层的气缝。

公开(公告)号：US10395980B1

公开(公告)日：2019-08-27

申请号：US15901411

申请日：2018-02-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Motoi Ichihashi ,  Atsushi Ogino

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a dual airgap structure and methods of manufacture. The structure includes: a lower metal line; a plurality of upper metal lines; and a first airgap between the lower metal line and at least one upper metal line of the plurality of upper metal lines.

公开(公告)号：US20180261538A1

公开(公告)日：2018-09-13

申请号：US15976300

申请日：2018-05-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Erdem Kaltalioglu ,  Atsushi Ogino

IPC: H01L23/528 ,  H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/28 ,  H01L21/283 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/48 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53295

Abstract: Disclosed herein is an integrated circuit (IC) including a first metal layer running in a first direction, a second metal layer running in a second direction perpendicular to the first direction, the second metal layer above the first metal layer and a third metal layer running in the first direction above the second metal layer. A viabar electrically connects the first metal layer to the third metal layer, the viabar running in the first direction wherein the viabar vertically extends from the first metal layer to the third metal layer. A method of manufacturing the IC is provided.

公开(公告)号：US09865473B1

公开(公告)日：2018-01-09

申请号：US15352139

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino

IPC: H01L21/311 ,  H01L21/033 ,  H01L23/00 ,  H01L27/02 ,  H01L27/11 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L21/3081 ,  H01L21/02164 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/3088 ,  H01L21/31144

Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first hardmask layer, a second hardmask layer, a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a set of islands; etching to define the set of islands, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.

公开(公告)号：US09748251B1

公开(公告)日：2017-08-29

申请号：US15352102

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Atsushi Ogino

IPC: H01L23/00 ,  H01L21/311 ,  H01L27/11 ,  H01L27/02 ,  H01L21/033

CPC classification number: H01L27/1116 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/11582 ,  H01L28/00

Abstract: Devices and methods of fabricating integrated circuit devices using semi-bidirectional patterning are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a dielectric layer, a first hardmask layer, a second hardmask layer, a third hardmask layer, and a lithography stack; patterning a first set of lines; patterning a second set of lines between the first set of lines; etching to define a combination of the first and second set of lines; depositing a second lithography stack; patterning a third set of lines in a direction perpendicular to the first and second set of lines; etching to define the third set of lines, leaving an OPL; depositing a spacer over the OPL; etching the spacer, leaving a vertical set of spacers; and etching the second hardmask layer using the third hardmask layer and the set of vertical spacers as masks.