- 专利标题: Vertical Transistor Device with a Variable Gate Dielectric Thickness
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申请号: US15957765申请日: 2018-04-19
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公开(公告)号: US20180248000A1公开(公告)日: 2018-08-30
- 发明人: Romain Esteve , Dethard Peters , Wolfgang Bergner , Ralf Siemieniec , Thomas Aichinger , Daniel Kueck
- 申请人: Infineon Technologies AG
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L29/16 ; H01L21/04 ; H01L29/10
摘要:
A vertical transistor device includes a silicon-carbide substrate, a gate trench formed in the silicon-carbide substrate, a body region adjacent the gate trench, a source region adjacent the gate trench and above the body region, and a dielectric material covering a bottom and a sidewall of the gate trench. A thickness of the dielectric material is greater at the bottom of the gate trench than along the sidewall of the gate trench. Further vertical transistor device embodiments and corresponding methods of manufacture are also described.
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