公开(公告)号：US10553685B2

公开(公告)日：2020-02-04

申请号：US15959661

申请日：2018-04-23

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Daniel Kueck

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.

公开(公告)号：US20170103894A1

公开(公告)日：2017-04-13

申请号：US15288349

申请日：2016-10-07

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Victorina Poenariu ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7813 ,  H01L29/8613

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.

公开(公告)号：US20150069411A1

公开(公告)日：2015-03-12

申请号：US14023819

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Jens Konrath ,  Daniel Kueck ,  David Laforet ,  Cedric Ouvrard ,  Roland Rupp ,  Andreas Voerckel ,  Wolfgang Werner

IPC: H01L29/78 ,  H01L29/812 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/0657 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/812 ,  H01L29/872

Abstract: A semiconductor device according to an embodiment is at least partially arranged in or on a substrate and includes a recess forming a mesa, wherein the mesa extends along a direction into the substrate to a bottom plane of the recess and includes a semiconducting material of a first conductivity type, the semiconducting material of the mesa including at least locally a first doping concentration not extending further into the substrate than the bottom plane. The semiconductor device further includes an electrically conductive structure arranged at least partially along a sidewall of the mesa, the electrically conductive structure forming a Schottky or Schottky-like electrical contact with the semiconducting material of the mesa, wherein the substrate comprises the semiconducting material of the first conductivity type comprising at least locally a second doping concentration different from the first doping concentration along a projection of the mesa into the substrate.

Abstract translation: 根据实施例的半导体器件至少部分地布置在衬底中或衬底上，并且包括形成台面的凹部，其中台面沿着进入衬底的方向延伸到凹部的底平面，并且包括第一 导电类型，台面的半导体材料至少局部地包括不比底平面进一步延伸到衬底中的第一掺杂浓度。 所述半导体器件还包括至少部分地沿着台面的侧壁布置的导电结构，该导电结构与台面的半导体材料形成肖特基或肖特基状的电接触，其中所述衬底包括所述半导体材料的半导体材料， 所述第一导电类型至少局部地包括沿所述台面的投影到所述衬底中的与所述第一掺杂浓度不同的第二掺杂浓度。

公开(公告)号：US10700182B2

公开(公告)日：2020-06-30

申请号：US15979050

申请日：2018-05-14

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: G06F30/398 ,  H01L29/66 ,  H01L29/739 ,  H01L27/02 ,  H01L29/16 ,  H01L29/78 ,  H01L29/861 ,  H01L21/66

Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.

公开(公告)号：US20180331204A1

公开(公告)日：2018-11-15

申请号：US15979050

申请日：2018-05-14

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/66 ,  G06F17/50 ,  H01L27/02

Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.

公开(公告)号：US20180308938A1

公开(公告)日：2018-10-25

申请号：US15959661

申请日：2018-04-23

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Daniel Kueck

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a trench extending from a first surface into a SiC semiconductor body. The trench has a first sidewall, a second sidewall opposite to the first sidewall, and a trench bottom. A gate electrode is arranged in the trench and is electrically insulated from the SiC semiconductor body by a trench dielectric. A body region of a first conductivity type adjoins the first sidewall. A shielding structure of the first conductivity type adjoins at least a portion of the second sidewall and the trench bottom. A first section of the trench bottom and a second section of the trench bottom are offset to one another by a vertical offset along a vertical direction extending from the first surface to a second surface of the SiC semiconductor body opposite to the first surface.

公开(公告)号：US20180248000A1

公开(公告)日：2018-08-30

申请号：US15957765

申请日：2018-04-19

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/10

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A vertical transistor device includes a silicon-carbide substrate, a gate trench formed in the silicon-carbide substrate, a body region adjacent the gate trench, a source region adjacent the gate trench and above the body region, and a dielectric material covering a bottom and a sidewall of the gate trench. A thickness of the dielectric material is greater at the bottom of the gate trench than along the sidewall of the gate trench. Further vertical transistor device embodiments and corresponding methods of manufacture are also described.

公开(公告)号：US09577073B2

公开(公告)日：2017-02-21

申请号：US14567504

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L21/324 ,  H01L21/04 ,  H01L21/02 ,  H01L21/311 ,  H01L29/16

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.

Abstract translation: 一种碳化硅半导体衬底，其具有多个第一掺杂区域，该第一掺杂区域在主表面之间彼此横向间隔开，并且形成从主表面延伸至位于第一掺杂区域之上的第三掺杂区域的第二掺杂区域 。 形成从主表面延伸到第一掺杂区的第四掺杂区。 形成具有布置在一个第一掺杂区域的一部分上的底部的栅极沟槽。 将高温步骤施加到衬底上，以便沿着沟槽的侧壁重新排列碳化硅原子，并在栅极沟槽中形成圆角。 去除在离开衬底的高温步骤期间沿着栅极沟槽的侧壁形成的表面层。

公开(公告)号：US11626477B2

公开(公告)日：2023-04-11

申请号：US17375034

申请日：2021-07-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component includes: gate structures extending from a first surface into an SiC semiconductor body; a drift zone of a first conductivity type formed in the SiC semiconductor body; first mesas and second mesas arranged between the gate structures in the SiC semiconductor body; body areas of a second conductivity type arranged in the first mesas and the second mesas, the body areas each adjoining a first side wall of one of the gate structures; first shielding areas of the second conductivity type adjoining a second side wall of one of the gate structures; second shielding areas of the second conductivity type adjoining the body areas in the second mesas; and diode areas of the conductivity type of the drift zone, the diode areas forming Schottky contacts with a load electrode between the first shielding areas and the second shielding areas.

公开(公告)号：US20190341447A1

公开(公告)日：2019-11-07

申请号：US16404284

申请日：2019-05-06

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/04 ,  H01L29/66 ,  H01L29/16

Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.