Invention Application
- Patent Title: SEMICONDUCTOR DEVICE CONTACTS WITH INCREASED CONTACT AREA
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Application No.: US15754887Application Date: 2015-09-25
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Publication No.: US20180248011A1Publication Date: 2018-08-30
- Inventor: RISHABH MEHANDRU , TAHIR GHANI , SZUYA S. LIAO
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US2015/052330 WO 20150925
- Main IPC: H01L29/417
- IPC: H01L29/417 ; H01L29/06 ; H01L29/423 ; H01L29/786 ; H01L29/78 ; H01L29/08 ; H01L29/66 ; H01L21/306 ; H01L21/265 ; H01L21/324 ; H01L21/768

Abstract:
Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.
Public/Granted literature
- US10896963B2 Semiconductor device contacts with increased contact area Public/Granted day:2021-01-19
Information query
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