公开(公告)号：US20180240874A1

公开(公告)日：2018-08-23

申请号：US15754150

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： CORY E. WEBER ,  SAURABH MORARKA ,  RITESH JHAVERI ,  GLENN A. GLASS ,  SZUYA S. LIAO ,  ANAND S. MURTHY

IPC: H01L29/08 ,  H01L21/225 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L21/2252 ,  H01L21/30612 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Techniques are disclosed for resistance reduction under transistor spacers. In some instances, the techniques include reducing the exposure of source/drain (S/D) dopants to thermal cycles, thereby reducing the diffusion and loss of S/D dopants to surrounding materials. In some such instances, the techniques include delaying the epitaxial deposition of the doped S/D material until near the end of the transistor formation process flow, thereby avoiding the thermal cycles earlier in the process flow. For example, the techniques may include replacing the S/D regions (e.g., native fin material in the regions to be used for the transistor S/D) with sacrificial S/D material that can then be selectively etched and replaced by highly doped epitaxial S/D material later in the process flow. In some cases, the selective etch may be performed through S/D contact trenches formed in overlying insulator material over the sacrificial S/D.

公开(公告)号：US20190355721A1

公开(公告)日：2019-11-21

申请号：US16473891

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  SCOTT J. MADDOX ,  RITESH JHAVERI ,  PRATIK A. PATEL ,  SZUYA S. LIAO ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

公开(公告)号：US20190355811A1

公开(公告)日：2019-11-21

申请号：US15983540

申请日：2018-05-18

Applicant: INTEL CORPORATION

Inventor： Rishabh Mehandru ,  Anupama Bowonder ,  Biswajeet Guha ,  Tahir Ghani ,  Stephen M. Cea ,  William Hsu ,  SZUYA S. LIAO ,  PRATIK A. PATEL

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is described that includes a first semiconductor layer conformally disposed on at least a portion of a source region and a second semiconductor layer conformally disposed on at least a portion of a drain region between the source/drain regions and corresponding gate spacers. The semiconductor layer can prevent diffusion and/or segregation of dopants from the source and drain regions into the gate spacers of the gate stack. Maintaining the intended location of dopant atoms in the source region and drain region improves the electrical characteristics of the semiconductor device including the external resistance (“Rext”) of the semiconductor device.

公开(公告)号：US20190279978A1

公开(公告)日：2019-09-12

申请号：US15754709

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  TAHIR GHANI ,  SZUYA S. LIAO ,  SEIYON KIM

IPC: H01L27/088 ,  H01L29/51 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/775

Abstract: Techniques are disclosed for forming nanowire transistor architectures in which the presence of gate material between neighboring nanowires is eliminated or otherwise reduced. In accordance with some embodiments, neighboring nanowires can be formed sufficiently proximate one another such that their respective gate dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous dielectric layer shared by the neighboring nanowires. In some cases, a given gate dielectric layer may be of a multi-layer configuration, having two or more constituent dielectric layers. Thus, in accordance with some embodiments, the gate dielectric layers of neighboring nanowires may be formed such that one or more constituent dielectric layers are either: (1) just in contact with one another (e.g., are contiguous); or (2) merged with one another to provide a single, continuous constituent dielectric layer shared by the neighboring nanowires.

公开(公告)号：US20190207015A1

公开(公告)日：2019-07-04

申请号：US16322815

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  CORY E. WEBER ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  JIONG ZHANG ,  RITESH JHAVERI ,  SZUYA S. LIAO

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

公开(公告)号：US20180248011A1

公开(公告)日：2018-08-30

申请号：US15754887

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  TAHIR GHANI ,  SZUYA S. LIAO

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/324 ,  H01L21/768

CPC classification number: H01L29/41766 ,  B82Y10/00 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/41733 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696

Abstract: Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.

公开(公告)号：US20170330972A1

公开(公告)日：2017-11-16

申请号：US15527288

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： GRANT KLOSTER ,  SCOTT CLENDENNING ,  Rami HOURANI ,  SZUYA S. LIAO ,  PATRICIO E. ROMERO ,  FLORIAN GSTREIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/786 ,  H01L23/498

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.