Invention Application
- Patent Title: 2-D Material Transistor with Vertical Structure
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Application No.: US16194018Application Date: 2018-11-16
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Publication No.: US20190103496A1Publication Date: 2019-04-04
- Inventor: Jean-Pierre COLINGE , Chung-Cheng WU , Carlos H. DIAZ , Chih-Hao WANG , Ken-Ichi GOTO , Ta-Pen GUO , Yee-Chia YEO , Zhiqiang WU , Yu-Ming LIN
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/786
- IPC: H01L29/786 ; H01L29/66 ; H01L29/78 ; H01L21/8238 ; H01L27/088 ; H01L21/02 ; H01L29/24 ; H01L29/16 ; H01L21/8256

Abstract:
Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.
Information query
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