公开(公告)号：US20150249141A1

公开(公告)日：2015-09-03

申请号：US14672298

申请日：2015-03-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Hsing YU ,  Chia-Wen LIU ,  Ken-Ichi GOTO

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/51 ,  H01L29/16 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66492 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833 ,  Y10S438/931

Abstract: A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.

Abstract translation: 提供晶体管和形成晶体管的方法。 该方法包括在晶体管沟道区域中执行至少一个注入操作，然后在引入另外的掺杂杂质之前在注入区上形成碳化硅/硅复合膜。 使用具有低倾斜角的光晕注入操作来在晶体管沟道的边缘处形成高掺杂浓度的区域，以减轻短沟道效应。 晶体管结构包括在与栅极电介质的衬底界面处的减少的掺杂剂杂质浓度和在表面下方约10-50nm的峰值浓度。 掺杂剂分布在晶体管沟道的相对端处具有高掺杂剂杂质浓度区域。

公开(公告)号：US20180175213A1

公开(公告)日：2018-06-21

申请号：US15615498

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Chung-Cheng WU ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Ken-Ichi GOTO ,  Ta-Pen GUO ,  Yee-Chia YEO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/16 ,  H01L29/24 ,  H01L21/02 ,  H01L21/8256

CPC classification number: H01L29/78696 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/823821 ,  H01L21/8256 ,  H01L27/0886 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/7851

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

公开(公告)号：US20180151700A1

公开(公告)日：2018-05-31

申请号：US15429335

申请日：2017-02-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ming LIN ,  Ken-Ichi GOTO

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/02 ,  H01L29/78 ,  H01L23/535 ,  H01L29/10 ,  H01L29/24 ,  H01L29/16

CPC classification number: H01L29/66795 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/1037 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first direction. A channel layer is formed on the fin structure. A gate stack including a gate electrode layer and a gate dielectric layer extending in a second direction perpendicular to the first direction is formed over the channel layer covering a portion of the length of the fin structure. The source and drain contacts are formed over trenches that extend into a portion of a height of the fin structure.

公开(公告)号：US20190097147A1

公开(公告)日：2019-03-28

申请号：US16201742

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Yu-Ming LIN ,  Ken-Ichi GOTO ,  Jean-Pierre COLINGE ,  Zhiqiang Wu

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US20150194485A1

公开(公告)日：2015-07-09

申请号：US14661237

申请日：2015-03-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Mahaveer Sathaiya DHANYAKUMAR ,  Wei-Hao WU ,  Tsung-Hsing YU ,  Chia-Wen LIU ,  Tzer-Min SHEN ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L29/0653 ,  H01L21/26586 ,  H01L21/76232 ,  H01L29/1033 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/78 ,  H01L29/7833

Abstract: A MOSFET disposed between shallow trench isolation (STI) structures includes an epitaxial silicon layer formed over a substrate surface and extending over inwardly extending ledges of the STI structures. The gate width of the MOSFET is therefore the width of the epitaxial silicon layer and greater than the width of the original substrate surface between the STI structures. The epitaxial silicon layer is formed over the previously doped channel and is undoped upon deposition. A thermal activation operation may be used to drive dopant impurities into the transistor channel region occupied by the epitaxial silicon layer but the dopant concentration at the channel location where the epitaxial silicon layer intersects with the gate dielectric, is minimized.

Abstract translation: 设置在浅沟槽隔离（STI）结构之间的MOSFET包括形成在衬底表面上并在STI结构的向内延伸的突出部上延伸的外延硅层。 因此，MOSFET的栅极宽度是外延硅层的宽度，并且大于STI结构之间的原始衬底表面的宽度。 外延硅层形成在预先掺杂的沟道上，并且在沉积时未被掺杂。 可以使用热激活操作来将掺杂剂杂质驱动到由外延硅层占据的晶体管沟道区域中，但是外延硅层与栅极电介质相交的沟道位置处的掺杂剂浓度最小化。

公开(公告)号：US20190019882A1

公开(公告)日：2019-01-17

申请号：US16128479

申请日：2018-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ming LIN ,  Ken-Ichi GOTO

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L29/10 ,  H01L29/16 ,  H01L29/24 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/0262 ,  H01L21/76805 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/1037 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device including a Fin FET device includes a fin structure protruding from a substrate layer and having a length extending in a first direction. A channel layer is formed on the fin structure. A gate stack including a gate electrode layer and a gate dielectric layer extending in a second direction perpendicular to the first direction is formed over the channel layer covering a portion of the length of the fin structure. The source and drain contacts are formed over trenches that extend into a portion of a height of the fin structure.

公开(公告)号：US20180366666A1

公开(公告)日：2018-12-20

申请号：US15627722

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Jean-Pierre COLINGE ,  Ken-Ichi GOTO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

CPC classification number: H01L51/057 ,  H01L51/0003 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/0558 ,  H01L51/105

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US20170210613A1

公开(公告)日：2017-07-27

申请号：US15007852

申请日：2016-01-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Ping CHEN ,  Carlos H. DIAZ ,  Ken-Ichi GOTO ,  Shau-Lin SHUE ,  Tai-I YANG

IPC: B81B3/00

CPC classification number: B81B3/0021 ,  B81B2203/0118 ,  B81B2207/015 ,  B81B2207/09 ,  B81C1/00246 ,  B81C2203/0136 ,  B81C2203/0771

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a substrate and an interconnect structure formed over the substrate. The NEMS device structure includes a dielectric layer formed over the interconnect structure and a beam structure formed in and over the dielectric layer. The beam structure includes a fixed portion and a moveable portion, the fixed portion is extended vertically, and the movable portion is extended horizontally. The NEMS device structure includes a cap structure formed over the dielectric layer and the beam structure and a cavity formed between the beam structure and the cap structure.

公开(公告)号：US20150162334A1

公开(公告)日：2015-06-11

申请号：US14624782

申请日：2015-02-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jon-Hsu HO ,  Chih-Ching WANG ,  Ching-Fang HUANG ,  Wen-Hsing HSIEH ,  Tsung-Hsing YU ,  Yi-Ming SHEU ,  Chih-Chieh YEH ,  Ken-Ichi GOTO ,  Zhiqiang WU

IPC: H01L27/088 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L27/0924 ,  H01L29/105 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/785 ,  H01L29/7851

Abstract: A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion.

Abstract translation: 形成包括半导体衬底的多栅极半导体器件。 多栅半导体器件还包括第一晶体管，其包括在半导体衬底之上延伸的第一鳍部。 第一晶体管具有形成在其中的第一沟道区。 第一沟道区域包括以第一掺杂剂类型的第一浓度掺杂的第一沟道区域部分和以第一掺杂剂类型的第二浓度掺杂的第二沟道区域部分。 第二浓度高于第一浓度。 第一晶体管还包括形成在第一沟道区上的第一栅电极层。 第一栅极电极层可以是第二掺杂剂类型。 第一掺杂剂类型可以是N型，第二掺杂剂类型可以是P型。 第二沟道区域部分可以形成在第一沟道区域部分上。

公开(公告)号：US20200299129A1

公开(公告)日：2020-09-24

申请号：US16895446

申请日：2020-06-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hsin-Ping CHEN ,  Carlos H. DIAZ ,  Ken-Ichi GOTO ,  Shau-Lin SHUE ,  Tai-I YANG

IPC: B82B1/00 ,  B81C1/00 ,  B81B3/00 ,  B82B3/00

Abstract: A NEMS device structure and a method for forming the same are provided. The NEMS device structure includes a first dielectric layer formed over a substrate, and a first conductive layer formed in the first dielectric layer. The NEMS device structure includes a second dielectric layer formed over the first dielectric layer, and a first supporting electrode a second supporting electrode and a beam structure formed in the second dielectric layer. The beam structure is formed between the first supporting electrode and the second supporting electrode, and the beam structure has a T-shaped structure. The NEMS device structure includes a first through hole formed between the first supporting electrode and the beam structure, and a second through hole formed between the second supporting electrode and the beam structure.