公开(公告)号：US20200333987A1

公开(公告)日：2020-10-22

申请号：US16921606

申请日：2020-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ ,  Ta-Pen GUO

IPC: G06F3/06 ,  H01L29/792 ,  H01L29/775 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L27/06 ,  H01L27/11578 ,  B82Y10/00 ,  G11C13/02 ,  G11C14/00 ,  G11C15/04 ,  H01L27/11514

Abstract: Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.

公开(公告)号：US20180175213A1

公开(公告)日：2018-06-21

申请号：US15615498

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Chung-Cheng WU ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Ken-Ichi GOTO ,  Ta-Pen GUO ,  Yee-Chia YEO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/16 ,  H01L29/24 ,  H01L21/02 ,  H01L21/8256

CPC classification number: H01L29/78696 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/823821 ,  H01L21/8256 ,  H01L27/0886 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/7851

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

公开(公告)号：US20200350173A1

公开(公告)日：2020-11-05

申请号：US16927942

申请日：2020-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L21/285 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/465 ,  H01L29/417 ,  H01L21/306 ,  H01L29/45

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US20180019339A1

公开(公告)日：2018-01-18

申请号：US15209224

申请日：2016-07-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/7851 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02592 ,  H01L21/02636 ,  H01L21/02667 ,  H01L21/26513 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

Abstract: Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a heavily-doped contact layer disposed between two adjacent layers. The heavily-doped contact layer may be formed through a solid-phase epitaxial regrowth method. The contact resistance may be tuned by adjusting dopant concentration and contact area configuration of the heavily-doped epitaxial contact layer.

公开(公告)号：US20180012769A1

公开(公告)日：2018-01-11

申请号：US15711542

申请日：2017-09-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/31 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The semiconductor device structure further includes a spacer element over a sidewall of the gate stack. The spacer element includes a first layer and a second layer over the first layer. The dielectric constant of the first layer is greater than the dielectric constant of the second layer. A gate dielectric layer of the gate stack adjoins the first layer and the second layer.

公开(公告)号：US20190103496A1

公开(公告)日：2019-04-04

申请号：US16194018

申请日：2018-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Chung-Cheng WU ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Ken-Ichi GOTO ,  Ta-Pen GUO ,  Yee-Chia YEO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L29/24 ,  H01L29/16 ,  H01L21/8256

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

公开(公告)号：US20180166533A1

公开(公告)日：2018-06-14

申请号：US15669064

申请日：2017-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ ,  Mark VAN DAL

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/465 ,  H01L29/24 ,  H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02568 ,  H01L21/02614 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/02628 ,  H01L21/02639 ,  H01L21/465 ,  H01L29/1033 ,  H01L29/24 ,  H01L29/66439 ,  H01L29/66969 ,  H01L29/785

Abstract: The present disclosure describes a method which can selectively etch silicon from silicon/silicon-germanium stacks or silicon-germanium from silicon-germanium/germanium stacks to form germanium-rich channel nanowires. For example, a method can include a multilayer stack formed with alternating layers of a silicon-rich material and a germanium-rich material. A first thin chalcogenide layer is concurrently formed on the silicon-rich material, and a second thick chalcogenide layer is formed on the germanium-rich material. The first chalcogenide layer and the second chalcogenide layer are etched until the first chalcogenide layer is removed from the silicon-rich material. The silicon-rich material and the second chalcogenide layer are etched with different etch rates.

公开(公告)号：US20180102252A1

公开(公告)日：2018-04-12

申请号：US15836448

申请日：2017-12-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L21/285 ,  H01L29/66 ,  H01L21/465 ,  H01L29/45 ,  H01L29/417 ,  H01L21/02 ,  H01L29/78 ,  H01L21/306 ,  H01L29/06

CPC classification number: H01L21/28518 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02667 ,  H01L21/30604 ,  H01L21/465 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US20190228977A1

公开(公告)日：2019-07-25

申请号：US16370521

申请日：2019-03-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jean-Pierre COLINGE ,  Carlos H. DIAZ

IPC: H01L21/285 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L29/45 ,  H01L29/78 ,  H01L21/465

Abstract: A semiconductor device includes a fin structure disposed over a substrate, a gate structure and a source. The fin structure includes an upper layer being exposed from an isolation insulating layer. The gate structure disposed over part of the upper layer of the fin structure. The source includes the upper layer of the fin structure not covered by the gate structure. The upper layer of the fin structure of the source is covered by a crystal semiconductor layer. The crystal semiconductor layer is covered by a silicide layer formed by Si and a first metal element. The silicide layer is covered by a first metal layer. A second metal layer made of the first metal element is disposed between the first metal layer and the isolation insulating layer.

公开(公告)号：US20180366666A1

公开(公告)日：2018-12-20

申请号：US15627722

申请日：2017-06-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Jean-Pierre COLINGE ,  Ken-Ichi GOTO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

CPC classification number: H01L51/057 ,  H01L51/0003 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/0558 ,  H01L51/105

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.