公开(公告)号：US20200041783A1

公开(公告)日：2020-02-06

申请号：US16517511

申请日：2019-07-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An LIU ,  Gwan-Sin CHANG ,  Bharath Kumar Pulicherla ,  Li-Jui CHEN ,  Sheng-Kang YU ,  Chung-Cheng WU ,  Zhiqiang WU

IPC: G02B27/00 ,  G21K1/06 ,  H05G2/00

Abstract: An EUV collector mirror for an extreme ultra violet (EUV) radiation source apparatus includes an EUV collector mirror body on which a reflective layer as a reflective surface is disposed, a trajectory correcting device attached to or embedded in the EUV collector mirror body and a trajectory correcting device to adjust the trajectory of metal from the reflective surface of the EUV collector mirror body to an opposite side of the EUV collector mirror body.

公开(公告)号：US20190103496A1

公开(公告)日：2019-04-04

申请号：US16194018

申请日：2018-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Chung-Cheng WU ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Ken-Ichi GOTO ,  Ta-Pen GUO ,  Yee-Chia YEO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L29/24 ,  H01L29/16 ,  H01L21/8256

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

公开(公告)号：US20200098923A1

公开(公告)日：2020-03-26

申请号：US16696845

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US20200098890A1

公开(公告)日：2020-03-26

申请号：US16559369

申请日：2019-09-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Li-Te LIN ,  Chung-Cheng WU ,  Gwan-Sin CHANG ,  Pinyen LIN

IPC: H01L29/66 ,  H01L21/311 ,  H01L29/40 ,  H01L29/78 ,  H01L29/49 ,  H01L21/3213

Abstract: A method includes forming a dummy gate over a substrate. A pair of gate spacers are formed on opposite sidewalls of the dummy gate. The dummy gate is removed to form a trench between the gate spacers. A first ion beam is directed to an upper portion of the trench, while leaving a lower portion of the trench substantially free from incidence of the first ion beam. The substrate is moved relative to the first ion beam during directing the first ion beam to the trench. A gate structure is formed in the trench.

公开(公告)号：US20180175213A1

公开(公告)日：2018-06-21

申请号：US15615498

申请日：2017-06-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jean-Pierre COLINGE ,  Chung-Cheng WU ,  Carlos H. DIAZ ,  Chih-Hao WANG ,  Ken-Ichi GOTO ,  Ta-Pen GUO ,  Yee-Chia YEO ,  Zhiqiang WU ,  Yu-Ming LIN

IPC: H01L29/786 ,  H01L27/088 ,  H01L29/16 ,  H01L29/24 ,  H01L21/02 ,  H01L21/8256

CPC classification number: H01L29/78696 ,  H01L21/02521 ,  H01L21/02527 ,  H01L21/02568 ,  H01L21/823821 ,  H01L21/8256 ,  H01L27/0886 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/7851

Abstract: Semiconductor structures including two-dimensional (2-D) materials and methods of manufacture thereof are described. By implementing 2-D materials in transistor gate architectures such as field-effect transistors (FETs), the semiconductor structures in accordance with this disclosure include vertical gate structures and incorporate 2-D materials such as graphene, transition metal dichalcogenides (TMDs), or phosphorene.

公开(公告)号：US20200294973A1

公开(公告)日：2020-09-17

申请号：US16889498

申请日：2020-06-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Zhi-Qiang WU ,  Chun-Fu CHENG ,  Chung-Cheng WU ,  Yi-Han WANG ,  Chia-Wen LIU

IPC: H01L25/065 ,  H01L21/02 ,  H01L25/04 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L27/06 ,  H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

公开(公告)号：US20190386114A1

公开(公告)日：2019-12-19

申请号：US16007885

申请日：2018-06-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-An LIU ,  Chan-Lon YANG ,  Bharath Kumar PULICHERLA ,  Zhi-Qiang WU ,  Chung-Cheng WU ,  Chih-Han LIN ,  Gwan-Sin CHANG

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: A semiconductor structure is disclosed that includes the fin structure and the plurality of gates. The plurality of gates disposed with respect to the fin structure and including the first gate, the second gate, and the third gate. The spacing between the first gate and the second gate is smaller than the spacing between the second gate and the third gate. The second gate is disposed between the first gate and the third gate. The foot portion of the first gate, facing the second gate, and the first foot portion of the second gate, facing the first gate, have no lateral extension. The second foot portion of the second gate, facing the third gate, and the foot portion of the third gate, facing the second gate, have no lateral extension and/or cut.

公开(公告)号：US20180301560A1

公开(公告)日：2018-10-18

申请号：US16016748

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/08

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

公开(公告)号：US20230197723A1

公开(公告)日：2023-06-22

申请号：US18168065

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ali KESHAVARZI ,  Ta-Pen GUO ,  Shu-Hui SUNG ,  Hsiang-Jen TSENG ,  Shyue-Shyh LIN ,  Lee-Chung LU ,  Chung-Cheng WU ,  Li-Chun TIEN ,  Jung-Chan YANG ,  Ting Yu CHEN ,  Min CAO ,  Yung-Chin HOU

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/49

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L23/485 ,  H01L27/0207 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/0649 ,  H01L29/495 ,  H01L2924/0002

Abstract: An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

公开(公告)号：US20220359754A1

公开(公告)日：2022-11-10

申请号：US17812997

申请日：2022-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Sheng WEI ,  Hung-Li CHIANG ,  Chia-Wen LIU ,  Yi-Ming SHEU ,  Zhiqiang WU ,  Chung-Cheng WU ,  Ying-Keung LEUNG

IPC: H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.