Invention Application
- Patent Title: CO-INTEGRATED CHANNEL AND GATE FORMATION SCHEME FOR NANOSHEET TRANSISTORS HAVING SEPARATELY TUNED THRESHOLD VOLTAGES
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Application No.: US16688222Application Date: 2019-11-19
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Publication No.: US20200083221A1Publication Date: 2020-03-12
- Inventor: Takashi Ando , Jingyun Zhang , Choonghyun Lee , Pouya Hashemi , Alexander Reznicek
- Applicant: International Business Machines Corporation
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/02 ; H01L29/49 ; H01L29/06 ; H01L29/786 ; H01L29/423 ; H01L21/28 ; H01L21/3215 ; H01L21/8238
Abstract:
Embodiments of the invention are directed to a configuration of nanosheet FET devices in a first region of a substrate. Each of the nanosheet FET devices in the first region includes a first channel nanosheet, a second channel nanosheet over the first channel nanosheet, a first gate structure around the first channel nanosheet, and a second gate structure around the second channel nanosheet, wherein the first gate structure and the second gate structure pinch off in a pinch off area between the first gate structure and the second gate structure. The first gate structure includes a doped region, and the second gate structure includes a doped region. At least a portion of the pinch off area is undoped.
Public/Granted literature
Information query
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