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公开(公告)号：US20230094719A1
公开(公告)日：2023-03-30
申请号：US17490454
申请日：2021-09-30
发明人： Cheng Chi , Takashi Ando , Reinaldo Vega , Praneet Adusumilli
摘要： A memory device is provided. The memory device includes a main feature disposed beneath a surface of a photolithographic mask. The memory device further includes at least one Sub-Resolution Assistant Feature (SRAF) proximate to the main feature beneath the surface. The main feature has an electrical conductivity based on an area relationship with the at least one SRAF.
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公开(公告)号：US20230085995A1
公开(公告)日：2023-03-23
申请号：US17481842
申请日：2021-09-22
发明人： Takashi Ando , Jonas Doevenspeck , Youngseok Kim , Soon-Cheon Seo , Seyoung Kim
摘要： A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.
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公开(公告)号：US20230077912A1
公开(公告)日：2023-03-16
申请号：US17475970
申请日：2021-09-15
发明人： Praneet Adusumilli , Kevin W. Brew , Takashi Ando , Reinaldo Vega
IPC分类号： H01L45/00
摘要： A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.
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公开(公告)号：US11605673B2
公开(公告)日：2023-03-14
申请号：US17116147
申请日：2020-12-09
IPC分类号： H01L27/24 , H01L27/092 , H01L45/00
摘要： An approach to forming a semiconductor structure is provided. The semiconductor structure includes two adjacent fins on a substrate. A gate stack is on each of the two adjacent fins. The semiconductor structure includes a first source/drain on a first end of each fin of the two adjacent fins and a second source/drain on a second end of each fin of the two adjacent fins. The semiconductor structure includes a switching layer on at least the first source/drain on the first end of each fin of the two adjacent fins and a top electrode on the switching layer. A metal material over the top electrode in the semiconductor structure.
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公开(公告)号：US20220393031A1
公开(公告)日：2022-12-08
申请号：US17336534
申请日：2021-06-02
发明人： Takashi Ando , Guy M. Cohen , Nanbo Gong
摘要： An approach for representing both positive and negative weights in neuromorphic computing is disclosed. The approach leverages a double gate FeFET (ferroelectric field effect transistor) device. The device leverages a double-gate FeFET with four terminals (two separate gates and source and drain) and ferroelectric gate dielectric. The device may have a junction-less channel. A synaptic weight is programmed by biasing one of the two gates. The store weight is sensed via a current flow from source to drain. A pre-defined bias is applied to the other gate during the sensing, such that a reference current is subtracted from the drain current. The net current for sensing is current from the synaptic devices subtracted by the pre-defined reference current.
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公开(公告)号：US20220392995A1
公开(公告)日：2022-12-08
申请号：US17341489
申请日：2021-06-08
发明人： Takashi Ando , REINALDO VEGA , David Wolpert , Cheng Chi , Praneet Adusumilli
摘要： A semiconductor device is provided. The semiconductor device includes: a first conductive electrode; a first dielectric stack structure provided on the first conductive electrode; a second conductive electrode provided on the first dielectric stack structure; a second dielectric stack structure provided on the second conductive electrode; and a third conductive electrode provided on the first dielectric stack structure, wherein each of the first dielectric stack structure and the second dielectric stack structure include a first dielectric layer comprising a first material; a second ferroelectric dielectric layer comprising a second material and provided on the first dielectric layer, and a third dielectric layer comprising a third material and provided on the second ferroelectric dielectric layer.
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公开(公告)号：US11515217B2
公开(公告)日：2022-11-29
申请号：US17166692
申请日：2021-02-03
发明人： Takashi Ando , Choonghyun Lee , Pouya Hashemi , Jingyun Zhang
IPC分类号： H01L27/082 , H01L21/8238 , H01L29/51 , H01L21/28 , H01L29/08 , H01L27/092 , H01L29/78 , H01L29/10 , H01L29/49
摘要： A method of forming a complementary metal oxide semiconductor (CMOS) device is provided. The method includes forming a separate gate structure on each of a pair of vertical fins, wherein the gate structures include a gate dielectric layer and a gate metal layer, and forming a protective liner layer on the gate structures. The method further includes heat treating the pair of gate structures, and replacing the protective liner layer with an encapsulation layer. The method further includes exposing a portion of the gate dielectric layer by recessing the encapsulation layer. The method further includes forming a top source/drain on the top surface of one of the pair of vertical fins, and subjecting the exposed portion of the gate dielectric layer to a second heat treatment conducted in an oxidizing atmosphere.
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公开(公告)号：US20220320428A1
公开(公告)日：2022-10-06
申请号：US17216937
申请日：2021-03-30
发明人： Guy M. Cohen , Takashi Ando , Nanbo Gong , Yulong Li
摘要： In an approach for forming a nonvolatile tunable capacitor device, a first electrode layer is formed distally opposed from a second electrode layer, the first electrode layer configured to make a first electrical connection and the second electrode layer configured to make a second electrical connection. A dielectric layer is posited between the first electrode layer and adjacent to the second electrode layer. A phase change material (PCM) layer is posited between the first electrode layer and the second electrode layer adjacent to the dielectric layer. An energizing component is provided to heat the PCM layer to change a phase of the PCM layer. The energizing component may include a heating element or electrical probe in direct contact with the PCM layer, that when energized is configured to apply heat to the PCM layer. The phase of the PCM layer is changeable between an amorphous phase and a crystalline phase.
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公开(公告)号：US11430954B2
公开(公告)日：2022-08-30
申请号：US17106286
申请日：2020-11-30
发明人： Praneet Adusumilli , Anirban Chandra , Takashi Ando , Cheng Chi , Reinaldo Vega
IPC分类号： H01L45/00
摘要： A mushroom-type Phase-Change Memory (PCM) device includes a substrate, a lower interconnect disposed in the substrate, a first dielectric layer disposed on the substrate, a bottom electrode disposed in the first dielectric layer and extending above an upper surface of the first dielectric layer, a type drift-mitigation liner encircling an upper portion of the bottom electrode extending above the upper surface of the first dielectric layer, a PCM element disposed on the liner and an upper surface of the bottom electrode, a top electrode disposed on the PCM element, and a second dielectric layer disposed on an exposed portion of the first dielectric layer and the top electrode, wherein the second dielectric layer is disposed on sidewalls of the liner, the PCM element, and the top electrode.
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公开(公告)号：US11379125B1
公开(公告)日：2022-07-05
申请号：US17218496
申请日：2021-03-31
摘要： An approach to creating a tamper-resistant field programmable gate array (FPGA) and remotely reprogramming the tamper-resistant FPGA. In one aspect, determining if an encryption key is stored in a physical unclonable function (PUF) of the FPGA. Further, responsive to the encryption key not being stored in a PUF, writing an encryption key in tamper resistant memory associated with a back end of the line (BEOL) of the FPGA. In another aspect, writing a program key and a look-up table (LUT) in the tamper resistant memory.
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