Invention Application
- Patent Title: Structure and Method for an MRAM Device with a Multi-Layer Top Electrode
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Application No.: US16510296Application Date: 2019-07-12
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Publication No.: US20200098978A1Publication Date: 2020-03-26
- Inventor: Wei-Hao Liao , Hsi-Wen Tien , Chih-Wei Lu , Pin-Ren Dai , Chung-Ju Lee
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L43/02
- IPC: H01L43/02 ; G11C11/16 ; H01L27/22 ; H01L43/12
Abstract:
A magnetic memory device includes a bottom electrode, a magnetic tunneling junction disposed over the bottom electrode, and a top electrode disposed over the magnetic tunneling junction, wherein the top electrode includes a first top electrode layer and a second top electrode layer above the first top electrode layer, and wherein the second top electrode layer is thicker than the first top electrode layer.
Public/Granted literature
- US11563167B2 Structure and method for an MRAM device with a multi-layer top electrode Public/Granted day:2023-01-24
Information query
IPC分类:
