Invention Application
- Patent Title: NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION
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Application No.: US16752612Application Date: 2020-01-24
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Publication No.: US20200159679A1Publication Date: 2020-05-21
- Inventor: Ramdas P. KACHARE , Fred WORLEY , Harry ROGERS , Wentao WU , Nagarajan SUBRAMANIYAN
- Applicant: Samsung Electronics Co., Ltd.
- Main IPC: G06F13/16
- IPC: G06F13/16 ; G06F13/42 ; G06F13/40

Abstract:
A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.
Public/Granted literature
- US11132310B2 SSD architecture for FPGA based acceleration Public/Granted day:2021-09-28
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