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公开(公告)号：US20240020001A1
公开(公告)日：2024-01-18
申请号：US18210641
申请日：2023-06-15
CPC分类号： G06F3/0604 , G06F11/3409 , G06F11/3452 , G06F11/3485 , G06F11/3419 , G06F11/3034 , G06F3/061 , G06F3/0653 , G06F2201/88
摘要： A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.
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公开(公告)号：US20220121261A1
公开(公告)日：2022-04-21
申请号：US17566658
申请日：2021-12-30
IPC分类号： G06F1/3209 , G06F13/16 , G06F3/06 , G06F13/40
摘要： A chassis is disclosed. The chassis may include a processor, a switch, and at least one storage device in communication with a remote processor. The storage device may support an active power mode and a low power mode. A response to a Keep Alive (KA) message may be sent to the remote processor on behalf of the storage device when the storage device is in low power mode.
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公开(公告)号：US20210318804A1
公开(公告)日：2021-10-14
申请号：US17356500
申请日：2021-06-23
摘要： A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.
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公开(公告)号：US20200004311A1
公开(公告)日：2020-01-02
申请号：US16111167
申请日：2018-08-23
摘要： A system is disclosed that provides emergency backup power to a solid-state drive (SSD) that may not contain any internal supercapacitors. The SSD may include a first connector and a hold-up power supply. The first connector may have a predetermined form factor and may being capable of being connected to a corresponding connector of a midplane of a storage system. The first connector may include a main power connection that is connected to a main power supply of the midplane if the first connector is connected to the corresponding connector of the midplane. The hold-up power supply may be internal to the SSD, and may receive hold-up energy from an external energy source for a predetermined amount of time after the first connector has been disconnected from the main power connection of the midplane so that the SSD may store any host data write requests that the SSD has acknowledged.
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公开(公告)号：US20190272240A1
公开(公告)日：2019-09-05
申请号：US16122865
申请日：2018-09-05
摘要： A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream interface enables communication with the processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.
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公开(公告)号：US20240320010A1
公开(公告)日：2024-09-26
申请号：US18732604
申请日：2024-06-03
发明人： Chao YANG , Wentao WU , Glenn YU , Wei ZHAO , FNU VIKRAM SINGH , Xiaoyi ZHANG , Yong YANG
CPC分类号： G06F9/3856 , G06F3/0611 , G06F3/0659 , G06F3/0673 , G06F9/30018 , G06F9/3834 , G06F9/544 , G06F11/3051
摘要： A method may include determining, with a queue availability module, that an entry is available in a queue, asserting a bit in a register based on determining that an entry is available in the queue, determining, with a processor, that the bit is asserted, and processing, with the processor, the entry in the queue based on determining that the bit is asserted. The method may further include storing the register in a tightly coupled memory associated with the processor. The method may further include storing the queue in the tightly coupled memory. The method may further include determining, with the queue availability module, that an entry is available in a second queue, and asserting a second bit in the register based on determining that an entry is available in the second queue. The method may further include finding the first bit in the register using a find first instruction.
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公开(公告)号：US20210182221A1
公开(公告)日：2021-06-17
申请号：US17187735
申请日：2021-02-26
摘要： A system is disclosed. An upstream interface enables communication with a processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for data, and a storage device acceleration module to assist the acceleration module in executing the acceleration instruction.
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公开(公告)号：US20210124681A1
公开(公告)日：2021-04-29
申请号：US17143153
申请日：2021-01-06
发明人： Wentao WU , Sompong OLARIG , William SCHWADERER , Ramdas KACHARE
IPC分类号： G06F12/0804 , G06F3/06
摘要： A storage system includes at least one solid-state drive (SSD) and a baseboard management controller (BMC). The at least one SSD communicates over a communication link information that the at least one SSD includes a predetermined number of super capacitors in which the predetermined number includes 0, and is capable of providing a mode of operation to flush data in a non-volatile memory to a non-volatile memory that spans a predetermined amount of time if a loss of power condition is detected. The BMC device receives the information from the SSD and in response sends a message to the at least on SSD to enter the mode of operation.
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公开(公告)号：US20200097176A1
公开(公告)日：2020-03-26
申请号：US16697177
申请日：2019-11-26
摘要： A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.
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公开(公告)号：US20190272241A1
公开(公告)日：2019-09-05
申请号：US16124179
申请日：2018-09-06
摘要： A system is disclosed. The system may include a processor running an application program and a memory storing data being used by the application program. An upstream port enables communication with the processor; a downstream port enables communication with a storage device. The system may also include an acceleration module implemented using hardware and including an Acceleration Platform Manager (APM-F) to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a physical function (PF) to expose the storage device, a second function to expose the acceleration module, a controller to manage operations of the storage device, storage for application data for the application program, and a storage device Acceleration Platform Manager (APM-S) to assist the APM-F in executing the acceleration instruction. A downstream filter associated with the downstream port may intercept an acceleration instruction associated with a downstream Filter Address Range (FAR) received from the storage device and deliver the acceleration instruction to the APM-F, the acceleration instruction being. An upstream filter associated with the upstream port may intercept an acceleration instruction received from the processor and deliver the second acceleration instruction to the APM-F. The processor, the acceleration module, and the storage device may communicate via a Peripheral Component Interconnect Exchange (PCIe) bus. The acceleration module may support performing the acceleration instruction on the application data on the storage device for the application program without loading the application data into the memory.
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