Invention Application
- Patent Title: DITHERED M BY N CLOCK DIVIDERS
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Application No.: US16269473Application Date: 2019-02-06
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Publication No.: US20200162083A1Publication Date: 2020-05-21
- Inventor: Sundarrajan RANGACHARI , Sriram MURALI , Sanjay PENNAM
- Applicant: TEXAS INSTRUMENTS INCORPORATED
- Priority: com.zzzhc.datahub.patent.etl.us.BibliographicData$PriorityClaim@2412b25c
- Main IPC: H03L7/197
- IPC: H03L7/197 ; G06F7/58 ; H03K21/02 ; H03K21/10 ; H03K3/84

Abstract:
A method for dithering a fractional clock divider includes generating a first clock enable sequence based on a seed pattern of M ones and N minus M zeros, selecting a cyclic rotation of the seed pattern after N input clock cycles, and generating a second clock enable sequence based on the cyclic rotation. A clock gate receives the input clock signal and the clock enable sequences and outputs M clock cycles for every N input clock cycles. A random number generator indicates the cyclic rotation of the seed pattern. The seed pattern can be replaced with an updated seed pattern of M ones and N minus M zeros in a different order. In some examples, the clock enable sequence is generated using a cyclic shift register containing the seed pattern and a multiplexor. In other examples, the clock enable sequence is generated using a modulo N counter and a comparator.
Public/Granted literature
- US10651863B1 Dithered M by N clock dividers Public/Granted day:2020-05-12
Information query
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