Invention Application
- Patent Title: CONDUCTIVE VIA AND METAL LINE END FABRICATION AND STRUCTURES RESULTING THEREFROM
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Application No.: US16637930Application Date: 2017-09-30
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Publication No.: US20200185271A1Publication Date: 2020-06-11
- Inventor: Charles H. WALLACE , Reken PATEL , Hyunsoo PARK , Mohit K. HARAN , Debashish BASU , Curtis W. WARD , Ruth A. Brain
- Applicant: Intel Corporation
- International Application: PCT/US2017/054641 WO 20170930
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/311 ; H01L23/522

Abstract:
Conductive via and metal line end fabrication is described. In an example, an interconnect structure includes a first inter-layer dielectric (ILD) on a hardmask layer, where the ILD includes a first ILD opening and a second ILD opening. The interconnect structure further includes an etch stop layer (ESL) on the ILD layer, where the ESL includes a first ESL opening aligned with the first ILD opening to form a first via opening, and where the ESL layer includes a second ESL opening aligned with the second ILD opening. The interconnect structure further includes a first via in the first via opening, a second ILD layer on the first ESL, and a metal line in the second ILD layer, where the metal line is in contact with the first via, and where the metal line includes a first metal opening, and where the metal line includes a second metal opening aligned with the second ILD opening and the ESL opening to form a second via opening. The interconnect structure further includes a metal line end in the first metal opening and further includes a second via in the metal line, where the second via is in the second via opening.
Public/Granted literature
- US11145541B2 Conductive via and metal line end fabrication and structures resulting therefrom Public/Granted day:2021-10-12
Information query
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